Microchip dsPIC33EP128MC506 Manual

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Analog-to-Digital

Converter (ADC)

Section 16. Analog-to-Digital Converter (ADC)

HIGHLIGHTS

This section of the manual contains the following major topics:

16.1 Introduction .................................................................................................................. 16-2

16.2 Control Registers .........................................................................................................16-6

16.3 Overview of Sample and Conversion Sequence ....................................................... 16-17

16.4 ADC Configuration ..................................................................................................... 16-28

16.5 ADC Interrupt Generation ..........................................................................................16-35

16.6 Analog Input Selection for Conversion....................................................................... 16-37

16.7 Specifying Conversion Results Buffering for Devices with DMA and with ADC DMA Enable

Bit (ADDMAEN) Set ................................................................................................... 16-52

16.8 ADC Configuration Example ...................................................................................... 16-56

16.9 ADC Configuration for 1.1 Msps ................................................................................ 16-57

16.10 Sample and Conversion Sequence Examples for Devices without DMA and for Devices

with DMA but with ADC DMA Enable Bit (ADDMAEN) Clear .................................... 16-59

16.11 Sample and Conversion Sequence Examples for Devices with DMA and with ADDMAEN

Bit Set ........................................................................................................................ 16-71

16.12 Configuration Examples for Devices with Internal Op Amps ..................................... 16-81

16.13 Analog-to-Digital Sampling Requirements ................................................................. 16-84

16.14 Reading the ADC Result Buffer ................................................................................. 16-85

16.15 Transfer Functions ..................................................................................................... 16-87

16.16 ADC Accuracy/Error................................................................................................... 16-89

16.17 Connection Considerations........................................................................................ 16-89

16.18 Operation During Sleep and Idle Modes.................................................................... 16-89

16.19 Effects of a Reset....................................................................................................... 16-90

16.20 Design Tips ................................................................................................................ 16-91

16.21 Related Application Notes.......................................................................................... 16-92

16.22 Revision History ......................................................................................................... 16-93

dsPIC33E/PIC24E Family Reference Manual

16.1 INTRODUCTION

This document describes the features and associated operational modes of the Successive

Approximation (SAR) Analog-to-Digital Converter (ADC) modules available on the

dsPIC33E/PIC24E families of devices.

This ADC module can be configured by the user application to function as a 10-bit, 4-channel

ADC or a 12-bit, single channel ADC.

On devices with Direct Memory Access (DMA), this ADC module can be configured to use DMA

or use a dedicated, 16-word memory mapped buffer instead of DMA.

An ADC module block diagram for devices without op amps is provided in Figure 16-1. The ADC

module block diagram for devices with op amps is provided in Figure 16-2.

The following key features are common to all dsPIC33E/PIC24E devices:

• SAR conversion

• Up to 1.1 Msps conversion speed in 10-bit mode

• Up to 500 ksps conversion speed in 12-bit mode

• Up to 32 analog input pins

• External voltage reference input pins

• Four unipolar, differential Sample-and-Hold (S&H) amplifiers

• Simultaneous sampling of up to four analog input pins

• Automatic Channel Scanning mode

• Selectable conversion trigger source

• Up to 16-word conversion result buffer

• Operation during CPU Sleep and Idle modes

Additional features are available on select dsPIC33E/PIC24E devices:

• Connections for up to three internal op amps (not available on all devices)

• Connections to the Charge Time Measurement Unit (CTMU) and temperature

measurement diode (not available on all devices)

• Channel selection and triggering can be controlled by the Peripheral Trigger Generator

(PTG) (not available on all devices)

• Selectable Buffer Fill modes (not available on all devices)

• DMA support, including Peripheral Indirect Addressing (PIA) (not available on all devices)

Depending on the device variant, the ADC module may have up to 49 analog input pins, designated

AN0-AN48, and four op amp outputs, designated OA1-OA3 and OA5. These analog inputs and

op amp outputs are connected by multiplexers to four S&H amplifiers, designated CH0-CH3. The

analog input multiplexers have two sets of control bits, designated as MUXA (CHySA/CHyNA) and

MUXB (CHySB/CHyNB). These control bits select a particular analog input for conversion. The

MUXA and MUXB control bits can alternatively select the analog input for conversion. Unipolar

differential conversions are possible on all channels using certain input pins.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all dsPIC33E/PIC24E devices.

Please consult the note at the beginning of the “Analog-to-Digital Converter

(ADC)” chapter in the current device data sheet to check whether this document

supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note: Op amps are not available on all devices. Refer to the “Op Amp/Comparator”

chapter in the specific device data sheet for availability.

Note: Refer to the “Analog-to-Digital Converter (ADC)” chapter in the specific device

data sheet to determine the availability of these additional features.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

Channel Scanning mode can be enabled for the CH0 S&H amplifier. Any subset of the analog

inputs or op amp outputs (based on availability) can be selected by the user application. The

selected inputs are converted in ascending order using CH0.

The ADC module supports simultaneous sampling using multiple S&H channels to sample the

inputs at the same time, and then performs the conversion for each channel sequentially. By

default, the multiple channels are sampled and converted sequentially.

For devices with DMA and with the ADC DMA Enable bit (ADDMAEN) set, the ADC module is

connected to a single-word result buffer. However, multiple conversion results can be stored in a

DMA RAM buffer with no CPU overhead when DMA is used with the ADC module. Each

conversion result is converted to one of four 16-bit output formats when it is read from the buffer.

For devices without DMA, and for devices with DMA that have the ADC DMA Enable bit

(ADDMAEN) clear, the ADC module is connected to a 16-word result buffer. The ADC result is

available in four different numerical formats (see Figure 16-14).

Note 1: A ‘y’ is used with MUXA and MUXB control bits to specify the S&H channel

numbers (y = 0 or 123). Refer to Section 16.6.2 “Alternate Input Selection

Mode” for more details.

2: Depending on a particular device pinout, the ADC can have up to 49 analog input

pins, designated AN0 through AN48, and four op amp outputs, designated

OA1-OA3 and OA5. In addition, there are two analog input pins for external voltage

reference connections (VREF+, VREF-). These analog inputs are shared with

op amp inputs and outputs, comparator inputs, and external voltage references.

When op amp/comparator functionality is enabled or an external voltage reference

is used, the analog input that shares that pin is no longer available. The actual

number of analog input pins and external voltage reference input configuration

depends on the specific device. For more details, refer to the specific device

data sheet.

dsPIC33E/PIC24E Family Reference Manual

Figure 16-1: ADC Block Diagram for dsPIC33E/PIC24E Devices without Op Amps

S&H0

S&H1

ADC1BUF0

ADC1BUF1(3)

ADC1BUF2(3)

ADC1BUFF(3)

ADC1BUFE(3)

AN0

AN311

AN1

VREFL

CH0SB<4:0>

(4)

CH0NA(4) CH0NB(4)

–

AN3

CH123SA

AN9

VREFL

CH123SB

CH123NA CH123NB

AN6

–

S&H2

AN5

CH123SA

AN10

VREFL

CH123SB

CH123NA CH123NB

AN7

–

S&H3

AN6

CH123SA

AN11

VREFL

CH123SB

CH123NA CH123NB

AN8

–

CH1

(2)

CH0

CH2

(2)

CH3

(2)

CH0SA<4:0>

Channel

Scan

CSCNA

Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For more details, refer to the specific device data sheet.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

3: These buffers are unavailable if DMA is available and the ADDMAEN bit is set.

4: These bits can be updated with Step commands from the PTG module (not available on all devices). Refer to the “Peripheral Trigger

Generator (PTG) Module” chapter in the specific device data sheet for availability.

REF

(1)

AV AVDD SSVREF-(1)

VCFG<2:0>

ALTS Alternate Input (MUXA/MUXB)

Selection

SAR ADC

VREFH VREFL

Figure 16-2: ADC Module Block Diagram with Connection Options for ANx Pins and Op Amps

VREFL

–

CH0

VREFL

AN0-ANx

OA1-OA3, OA5

CH0Sx

CH0Nx

CH123Nx

00000

11111

CH0SA<5:0>(3)

CH0SB<5:0>(3)

CH0NA(3)

CH0NB(3)

CH123SA<2:0>

CH123SB<2:0>

CH123NA<1:0>

CH123NB<1:0>

S&H1

Channel Scan

This diagram depicts all of the available

ADC connection options to the four S&H

amplifiers, which are designated: CH0,

CH1, CH2 and CH3.

The ANx analog pins or op amp outputs are

connected to the CH0-CH3 amplifiers

through the multiplexers, controlled by the

SFR control bits, CH0Sx, CH0Nx, CH123Sx

and CH123Nx.

–

CH1

–

CH2

–

CH3

CH123x

–OA2 CH123Sx

CH123Nx

–OA3

CH123Sx

AN0/OA2OUT/RA0

PGEC1/AN4/C1IN1+/RPI34/RB2

PGED1/AN5/C1IN1-/RP35/RB3

PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1

AN9/RPI27/RA11

AN1/C2IN1+/RA1

AN10/RPI28/RA12

PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0

AN8/C3IN1+/U1RTS/BCLK1/RC2

AN6/OA3OUT/C4IN1+/OCFB/RC0

AN7/C3IN1-/C4IN1-/RC1

AN11/C1IN2-/U1CTS/RC11

–OA1

REF

(1)

REF

VCFG<2:0>

From CTMU

Current Source (CTMUI)

CTMU TEMP

S&H2

S&H3

S&H0

Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

3: These bits can be updated with Step commands from the PTG module. For more information, refer to the “Peripheral Trigger Generator (PTG)” chapter in the sp

4: When ADDMAEN (ADxCON4<8>) = 1 enabling DMA, only ADCxBUF0 is used.

OPEN

ALTS

000

001

010

011

1xx

000

001

010

011

1xx

–

OA5

000

001

010

011

1xx

OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4

TMS/OA5IN-/AN27/C5IN1-/RP41/RB9

OA5OUT/AN25/C5IN4-/RP39/INT0/RB7

SAR ADC

VREFH

dsPIC33E/PIC24E Family Reference Manual

16.2 CONTROL REGISTERS

The ADC module has nine Control and Status registers:

• ADxCON1: ADCx Control Register 1

• ADxCON2: ADCx Control Register 2

• ADxCON3: ADCx Control Register 3

• ADxCON4: ADCx Control Register 4

•ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register

•ADxCHS0: ADCx Input Channel 0 Select Register

•ADxCSSH: ADCx Input Scan Select Register High

•ADxCSSL: ADCx Input Scan Select Register Low

•ANSELy: Analog/Digital Pin Selection Register

The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.

For devices with DMA, the ADxCON4 register sets up the number of conversion results stored

in a DMA buffer for each analog input in the Scatter/Gather mode. The ADxCHS123 and

ADxCHS0 registers select the input pins to be connected to the S&H amplifiers. The ADCSSH/L

registers select inputs to be sequentially scanned. The ANSELy register specifies the input

collection of device pins used as analog inputs. Along with the Data Direction register (TRISx) in

the Parallel I/O Port module, ANSELy registers control the operation of the ADC pins.

16.2.1 ADC Result Buffer

For devices with DMA and with the ADC DMA Enable bit (ADDMAEN) set, the ADC module

contains a single-word result buffer, ADC1BUF0. For devices without DMA, and for devices with

DMA that have the ADC DMA Enable bit (ADDMAEN) clear, the ADC module contains a 16-word

dual port RAM to buffer the results. The 16 buffer locations are referred to as ADC1BUF0,

ADC1BUF1, ADC1BUF2, ..., ADC1BUFE and ADC1BUFF.

Note: After a device Reset, the ADC Buffer register(s) will contain unknown data.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0U-0

ADON — ADSIDL ADDMABM( )1— AD12B( )1FORM<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0, HC, HS R/C-0, HC, HS

SSRC<2:0> SSRCG SIMSAM ASAM( )2SAMP DONE( )2

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit

R = Readable bit U = Unimplemented bit, read as ‘0’W = Writable bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: ADC Operating Mode bit

1 = ADC module is operating

0 = ADC is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: ADC Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12 ADDMABM: DMA Buffer Build Mode bit( )1

1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA channel

that is the same as the address used for the non-DMA stand-alone buffer

0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather mode

address to the DMA channel, based on the index of the analog input and the size of the DMA buffer

bit 11 Unimplemented: Read as ‘0’

bit 10 AD12B: ADC 10-Bit or 12-Bit Operation Mode bit

( )1

1 = 12-bit, 1-channel ADC operation

0 = 10-bit, 4-channel ADC operation

bit 9-8 FORM<1:0>: Data Output Format bits

For 10-Bit Operation:

11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s d = sign, = data)

10 dddd dddd dd00 0000 = Fractional (DOUT = )

01 = Signed integer (DOUT = ssss sssd dddd dddd , where s = sign, d = data)

00 = Integer (DOUT = 0000 00dd dddd dddd )

For 12-Bit Operation:

11 = Signed fractional (DOUT = sddd dddd dddd 0000 , where s = sign, d = data)

10 dddd dddd dddd 0000 = Fractional (DOUT = )

01 = Signed Integer (DOUT = ssss sddd dddd dddd , where s = sign, d = data)

00 = Integer (DOUT = 0000 dddd dddd dddd )

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits

These settings vary by device. Refer to the ADxCON1 register in the “Analog-to-Digital Converter

(ADC)” chapter in the specific device data sheet for availability.

bit 4 SSRCG: Sample Clock Source Group bit

These settings vary by device. Refer to the ADxCON1 register in the “Analog-to-Digital Converter

(ADC)” chapter in the specific device data sheet for availability.

Note 1: This bit or setting is not available on all devices. Refer to the “Analog-to-Digital Converter (ADC)”

chapter in the specific device data sheet for availability.

2: Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1).

dsPIC33E/PIC24E Family Reference Manual

bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)

In 12-bit mode (AD21B = 1), SIMSAM is unimplemented and is read as ‘0’.

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or samples CH0 and CH1

simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2 ASAM: ADC Sample Auto-Start bit( )2

1 = Sampling begins immediately after last conversion; SAMP bit is auto-set

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

1 = ADC Sample-and-Hold amplifiers are sampling

0 = ADC Sample-and-Hold amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC<2:0> = and SSRCG = 000 0, software can write ‘0’ to end sampling and start conversion. If

SSRC<2:0> 000, automatically cleared by hardware to end sampling and start conversion.

bit 0 DONE: ADC Conversion Status bit( )2

1 = ADC conversion cycle has completed

0 = ADC conversion has not started or is in progress

Automatically set by hardware when Analog-to-Digital conversion is complete. Software can write ‘0’ to

clear the DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation

in progress. Automatically cleared by hardware at the start of a new conversion.

Note 1: This bit or setting is not available on all devices. Refer to the “Analog-to-Digital Converter (ADC)”

chapter in the specific device data sheet for availability.

2: Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1).

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 U-0 U-0

VCFG<2:0> — — CSCNA CHPS<1:0>

bit 15 bit 8

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS SMPI<4:0>( , , )123 BUFM ALTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: ADC Converter Voltage Reference Configuration bits

bit 12-11 Unimplemented: Read as ‘0’

bit 10 CSCNA: Input Scan Select bit

1 = Scans inputs for CH0+ during Sample A bit

0 = Does not scan inputs

bit 9-8 CHPS<1:0>: Channel Select bits

When AD12B = 1, CHPS<1:0> is: U-0 (Unimplemented: Read as ‘0’)

1x = Converts CH0, CH1, CH2 and CH3

01 = Converts CH0 and CH1

00 = Converts CH0

bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)

1 = ADC is currently filling the second half of the buffer; the user application should access data in the

first half of the buffer

0 = ADC is currently filling the first half of the buffer; the user application should access data in the

second half of the buffer

Note 1: For devices with DMA and with the ADC DMA Enable bit (ADDMAEN) set, the SMPI<4:0> bits are referred

to as the “Increment Rate for DMA Address Select bits”.

2: For devices without DMA, and for devices with DMA that have the ADC DMA Enable bit (ADDMAEN) clear,

the SMPI<4:0> bits are referred to as the “Number of Samples per Interrupt Select bits”.

3: For ADC2, the sample and conversion operation bits are only four bits (SMPI<3:0>), which provide an ADC

interrupt (for devices without DMA), and incrementation of the DMA address (for devices with DMA) at the

completion of up to16 sample and conversion operations.

VREFH VREFL

000 AV AVDD SS

001 External VREF+ AVSS

010 AVDD External VREF-

011 External VREF+ External VREF-

1xx AV AVDD SS

dsPIC33E/PIC24E Family Reference Manual

bit 6-2 SMPI<4:0>: Sample and Conversion Operation bits( , , )123

For Devices with DMA and with the ADC DMA Enable bit (ADDMAEN) Set:

x1111 = Increments the DMA address after completion of every 16th sample/conversion operation

x1110 = Increments the DMA address after completion of every 15th sample/conversion operation

•

x0001 = Increments the DMA address after completion of every 2nd sample/conversion operation

x0000 = Increments the DMA address after completion of every sample/conversion operation

For Devices without DMA and for Devices with DMA that have the ADC DMA Enable bit (ADDMAEN) Clear:

11111 = ADC interrupt is generated at the completion of every 32nd sample/conversion operation

11110 = ADC interrupt is generated at the completion of every 31st sample/conversion operation

•

00001 = ADC interrupt is generated at the completion of every 2nd sample/conversion operation

00000 = ADC interrupt is generated at the completion of every sample/conversion operation

bit 1 BUFM: Buffer Fill Mode Select bit

1 = Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer

on the next interrupt

0 = Always starts filling the buffer from the Start address

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample MUXA on first sample and Sample MUXB on next sample

0 = Always uses channel input selects for Sample MUXA

Note 1: For devices with DMA and with the ADC DMA Enable bit (ADDMAEN) set, the SMPI<4:0> bits are referred

to as the “Increment Rate for DMA Address Select bits”.

2: For devices without DMA, and for devices with DMA that have the ADC DMA Enable bit (ADDMAEN) clear,

the SMPI<4:0> bits are referred to as the “Number of Samples per Interrupt Select bits”.

3: For ADC2, the sample and conversion operation bits are only four bits (SMPI<3:0>), which provide an ADC

interrupt (for devices without DMA), and incrementation of the DMA address (for devices with DMA) at the

completion of up to16 sample and conversion operations.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0U-0 U-0

ADRC — — SAMC<4:0>( , )1 2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

ADCS<7:0>( )3

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: ADC Conversion Clock Source bit

1 = ADC internal RC clock

0 = Clock derived from system clock

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto-Sample Time bits( , )1 2

11111 = 31 TAD

•

00001 = 1 TAD

00000 = 0 TAD

bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits( )3

11111111 = TCY • (ADCS<7:0> + 1) = 256 • TCY = TAD

•

00000010 = TCY • (ADCS<7:0> + 1) = 3 • TCY = TAD

00000001 = TCY • (ADCS<7:0> + 1) = 2 • TCY = TAD

00000000 = TCY • (ADCS<7:0> + 1) = 1 • TCY = TAD

Note 1: These bits are only used when the SSRC<2:0> bits (ADxCON1<7:5>) = 111 and SSRCG = 0.

2: If SSRC<2:0> = 111 and SSRCG = 0, the SAMC<4:0> bits should be set to at least ‘11111’ when using

one S&H channel or using simultaneous sampling. When using multiple S&H channels with sequential

sampling, the SAMCx bits should be set to ‘00000’ for the fastest possible conversion rate.

3: These bits are not used if the ADRC bit (ADxCON3<15>) = 1.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — CH123SB<2:1> CH123NB<1:0> CH123SB0

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — CH123SA<2:1> CH123NA<1:0> CH123SA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-11 CH123SB<2:1>: Channels 1, 2, 3 Positive Input Select for Sample B bits

bit 10-9 CH123NB<1:0>: Channels 1, 2, 3 Negative Input Select for Sample B bits

bit 8 CH123SB0: Channels 1, 2, 3 Positive Input Select for Sample B bit

bit 7-5 Unimplemented: Read as ‘0’

bit 4-3 CH123SA<2:1>: Channels 1, 2, 3 Positive Input Select for Sample A bits

bit 2-1 CH123NA<1:0>: Channels 1, 2, 3 Negative Input Select for Sample A bits

bit 0 CH123SA0: Channels 1, 2, 3 Positive Input Select for Sample A bit

Note: The bit settings in this register vary by device. Refer to the ADxCHS123 register in the “Analog-to-Digital

Converter (ADC)” chapter in the specific device data sheet for availability.

dsPIC33E/PIC24E Family Reference Manual

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0U-0

CH0NB — CH0SB<5:0>( )1

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0U-0

CH0NA — CH0SA<5:0>( )1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit

bit 14 Unimplemented: Read as ‘0’

bit 13-8 CH0SB<5:0>: Channel 0 Positive Input Select for Sample B bits

( )1

bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit

bit 6 Unimplemented: Read as ‘0’

bit 5-0 CH0SA<5:0>: Channel 0 Positive Input Select for Sample A bits

( )1

Note 1: These bits have no effect when the CSCNA bit (ADxCON2<10>) = 1.

Note: The bit settings in this register vary by device. Refer to the ADxCHS0 register in the “Analog-to-Digital

Converter (ADC)” chapter in the specific device data sheet for availability.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<31:16>: ADC Input Scan Selection bits

1 = Selects ANx for input scan

0 = Skips ANx for input scan

Note: Refer to the “Analog-to-Digital Converter (ADC)” chapter in the specific device data sheet for availability

of channel scan selections.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

CSS15 CSS14 CSS13 CSS12 CSS11 CSS9 CSS8CSS10

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<15:0>: ADC Input Scan Selection bits

1 = Selects ANx for input scan

0 = Skips ANx for input scan

Note: Refer to the “Analog-to-Digital Converter (ADC)” chapter in the specific device data sheet for availability

of channel scan selections.

dsPIC33E/PIC24E Family Reference Manual

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1R/W-1

ANSy15 ANSy13 ANSy11 ANSy10 ANSy9 ANSy8ANSy14 ANSy12

bit 15 bit 8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1R/W-1

ANSy7 ANSy6 ANSy5 ANSy3 ANSy2 ANSy1 ANSy0ANSy4

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 ANSy<15:0>: Analog/Digital Pin Selection bits

1 = Pin is configured as an analog input

0 = Pin is configured as a digital I/O pin

Note: Refer to the “I/O Ports” chapter in the specific device data sheet for availability of I/O ports. The ‘y’ in

ANSELy refers to PORTA, PORTB, PORTC, etc.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

16.3 OVERVIEW OF SAMPLE AND CONVERSION SEQUENCE

Figure 16-3 illustrates the three-step process of the Analog-to-Digital conversion:

1. The input voltage signal is connected to the sample capacitor.

2. The sample capacitor is disconnected from the input.

3. The stored voltage is converted to equivalent digital bits.

The two distinct phases, sample and convert, are independently controlled.

Figure 16-3: Sample Conversion Sequence

16.3.1 Sample Time

Sample time is when the selected analog input is connected to the sample capacitor. There is a

minimum sample time to ensure that the S&H amplifier provides a desired accuracy for the

Analog-to-Digital conversion (see Section 16.13 “Analog-to-Digital Sampling Requirements”).

The sampling phase can be set up to start automatically upon conversion or by manually setting

the Sample bit (SAMP) in the ADC Control Register 1 (ADxCON1<1>). The sampling phase is

controlled by the Auto-Sample bit (ASAM) in the ADC Control Register 1 (ADxCON1<2>).

Table 16-1 lists the options selected by the specific bit configuration.

Table 16-1: Start of Sampling Selection

If automatic sampling is enabled, the Sampling Time (TSMP) taken by the ADC module is equal

to the number of TAD cycles defined by the SAMC<4:0> bits (ADxCON3<12:8>), as shown in

Equation 16-1.

Equation 16-1: Sampling Time Calculation

If manual sampling is desired, the user software must provide sufficient time to ensure adequate

sampling time.

–

Sample Time Conversion Time

SOC

Trigger

SAR

ADC

Note: The ADC module requires a finite number of Analog-to-Digital clock cycles to start

conversion after receiving a conversion trigger or ending the sampling process. For

more details, refer to the TPCS parameter in the “Electrical Characteristics”

chapter of the specific device data sheet.

ASAM Start of Sampling Selection

0Manual Sampling

1Automatic Sampling

TSMP = SAMC<4:0> • TAD

dsPIC33E/PIC24E Family Reference Manual

16.3.2 Conversion Time

The Start of Conversion (SOC) trigger ends the sampling time and begins an Analog-to-Digital

conversion. During the conversion period, the sample capacitor is disconnected from the

multiplexer and the stored voltage is converted to equivalent digital bits. The conversion times

for 10-bit and 12-bit modes are shown in Equation 16-2 and Equation 16-3 . The sum of the

sample time and the Analog-to-Digital conversion time provides the total conversion time.

For correct Analog-to-Digital conversion, the Analog-to-Digital Conversion Clock (TAD) must be

selected to ensure a minimum TAD time. Refer to the “Electrical Characteristics” chapter of the

specific device data sheet for the minimum TAD specifications for 10-bit and 12-bit modes.

Equation 16-2: 10-Bit ADC Conversion Time

Equation 16-3: 12-Bit ADC Conversion Time

The SOC can be triggered by a variety of hardware sources or controlled manually in user soft-

ware. The trigger source to initiate conversion is selected by the SOC Trigger Source Select bits

(SSRC<2:0>) in the ADCx Control Register 1 (ADxCON1<7:5>). The Sample Clock Source

Group bit, SSRCG (ADxCON1<4>), selects between the two groups. The SSRCx bits provide

different sample clock sources based on the group selected.

Table 16-2 lists the sample conversion sequence with different sample and conversion phase

selections.

Table 16-2: Sample Conversion Sequence Selection

Note: Refer to the “Analog-to-Digital Converter (ADC)” chapter in the specific device

data sheet for the available SOC trigger sources.

TCONV = 12 • TAD

Where:

TCONV = Conversion Time

TAD = ADC Clock Period

Where:

TCONV = Conversion Time

TCONV = 14 • TAD

TAD = ADC Clock Period

ASAM SSRCG SSRC<2:0> Description

0 0 000 Manual Sample and Manual Conversion Sequence

0 0 111 Manual Sample and Automatic Conversion Sequence

0 0 1 or 001

010

011

100

Manual Sample and Triggered Conversion Sequence

1 000

111

1 0 000 Automatic Sample and Manual Conversion Sequence

1 0 111 Automatic Sample and Automatic Conversion

Sequence

1 0 1 or 001

010

011

100

Automatic Sample and Triggered Conversion

Sequence

1 000

111

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

16.3.3 Manual Sample and Manual Conversion Sequence

In the Manual Sample and Manual Conversion Sequence, setting the Sample bit (SAMP) in the

ADCx Control Register 1 (ADxCON1<1>) initiates sampling, and clearing the SAMP bit

terminates sampling and starts the conversion (see Figure 16-4). The user application must time

the setting and clearing of the SAMP bit to ensure adequate sampling time for the input signal.

Example 16-1 shows a code sequence for Manual Sample and Manual Conversion.

Figure 16-4: Manual Sample and Manual Conversion Sequence

Sample Time Conversion Time

SAMP

Sample Time

3 4

Conversion

Note 1: Sampling starts by setting the SAMP bit (ADxCON1<1>) in software.

2: Conversion starts by clearing the SAMP bit in software.

3: Conversion is complete.

4: Sampling starts by setting the SAMP bit in software.

5: Conversion starts by clearing the SAMP bit in software.

–

dsPIC33E/PIC24E Family Reference Manual

Example 16-1: Code Sequence for Manual Sample and Manual Conversion

#include <p33Exxxx.h>

/****************************CONFIGURATION****************************/

_FOSCSEL(FNOSC_FRC);

_FOSC(FCKSM_CSECMD & POSCMD_XT & OSCIOFNC_OFF & IOL1WAY_OFF);

_FWDT(FWDTEN_OFF);

_FPOR(FPWRT_PWR128 & BOREN_ON & ALTI2C1_ON & ALTI2C2_ON);

_FICD(ICS_PGD1 & RSTPRI_PF & JTAGEN_OFF);

void initAdc1(void);

void Delay_us(unsigned int);

int ADCValue, i;

int main(void)

{

// Configure the device PLL to obtain 40 MIPS operation. The crystal frequency is 8 MHz.

// Divide 8 MHz by 2, multiply by 40 and divide by 2. This results in Fosc of 80 MHz.

// The CPU clock frequency is Fcy = Fosc/2 = 40 MHz.

PLLFBD = 38; /* M = 40 */

CLKDIVbits.PLLPOST = 0; /* N1 = 2 */

CLKDIVbits.PLLPRE = 0; /* N2 = 2 */

OSCTUN = 0;

/* Initiate Clock Switch to Primary Oscillator with PLL (NOSC = 0x3) */

__builtin_write_OSCCONH(0x03);

__builtin_write_OSCCONL(0x01);

while (OSCCONbits.COSC != 0x3);

while (_LOCK == 0); /* Wait for PLL lock at 40 MIPS */

initAdc1();

while(1)

{

AD1CON1bits.SAMP = 1; // Start sampling

Delay_us(10); // Wait for sampling time (10 us)

AD1CON1bits.SAMP = 0; // Start the conversion

while (!AD1CON1bits.DONE); // Wait for the conversion to complete

ADCValue = ADC1BUF0; // Read the ADC conversion result

}

void initAdc1(void)

{

/* Set port configuration */

ANSELA = ANSELB = ANSELC = ANSELD = ANSELE = ANSELG = 0x0000;

ANSELBbits.ANSB5 = 1; // Ensure AN5/RB5 is analog

/* Initialize and enable ADC module */

AD1CON1 = 0x0000;

AD1CON2 = 0x0000;

AD1CON3 = 0x000F;

AD1CON4 = 0x0000;

AD1CHS0 = 0x0005;

AD1CHS123 = 0x0000;

AD1CSSH = 0x0000;

AD1CSSL = 0x0000;

AD1CON1bits.ADON = 1;

Delay_us(20);

}

void Delay_us(unsigned int delay)

{

for (i = 0; i < delay; i++)

{

__asm__ volatile ("repeat #39");

__asm__ volatile ("nop");

}

Note: Due to the internal delay within the ADC module, the SAMP bit (ADxCON1<1>) will read as ‘0’ to the user

software. This change occurs in a small interval of time after the conversion has started. In general, the

time interval is 2 TCY.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

16.3.4 Automatic Sample and Manual Conversion Sequence

In the Automatic Sample and Manual Conversion Sequence, sampling starts automatically after

conversion of the previous sample. The user application must allocate sufficient time for

sampling before clearing the SAMP bit (ADxCON1<1>). Clearing the SAMP bit initiates the

conversion (see Figure 16-5).

Figure 16-5: Automatic Sample and Manual Conversion Sequence

Sample Time Conversion Time

SAMP

Sample Time

Conversion

Note 1: Sampling starts automatically after conversion completion of the previous sample.

2: Conversion starts by clearing the SAMP bit (ADxCON1<1>) in software.

3: Conversion is complete. Sampling starts automatically after conversion completion of the previous sample.

4: Conversion starts by clearing the SAMP bit in software.

–

dsPIC33E/PIC24E Family Reference Manual

Example 16-2: Code Sequence for Automatic Sample and Manual Conversion

#include <p33Exxxx.h>

/****************************CONFIGURATION****************************/

_FOSCSEL(FNOSC_FRC);

_FOSC(FCKSM_CSECMD & POSCMD_XT & OSCIOFNC_OFF & IOL1WAY_OFF);

_FWDT(FWDTEN_OFF);

_FPOR(FPWRT_PWR128 & BOREN_ON & ALTI2C1_ON & ALTI2C2_ON);

_FICD(ICS_PGD1 & RSTPRI_PF & JTAGEN_OFF);

void initAdc1(void);

void Delay_us(unsigned int);

int ADCValue, i, j;

int main(void)

{

// Configure the device PLL to obtain 40 MIPS operation. The crystal frequency is 8 MHz.

// Divide 8 MHz by 2, multiply by 40 and divide by 2. This results in Fosc of 80 MHz.

// The CPU clock frequency is Fcy = Fosc/2 = 40 MHz.

PLLFBD = 38; /* M = 40 */

CLKDIVbits.PLLPOST = 0; /* N1 = 2 */

CLKDIVbits.PLLPRE = 0; /* N2 = 2 */

OSCTUN = 0;

/* Initiate Clock Switch to Primary Oscillator with PLL (NOSC = 0x3) */

__builtin_write_OSCCONH(0x03);

__builtin_write_OSCCONL(0x01);

while (OSCCONbits.COSC != 0x3);

while (_LOCK == 0); /* Wait for PLL lock at 40 MIPS */

initAdc1();

while(1)

{

Delay_us(100); // Sample for 100 us

AD1CON1bits.SAMP = 0; // Start the conversion

while (!AD1CON1bits.DONE); // Wait for the conversion to complete

AD1CON1bits.DONE = 0; // Clear conversion done status bit

ADCValue = ADC1BUF0; // Read the ADC conversion result

}

void initAdc1(void)

{

/* Set port configuration */

ANSELA = ANSELB = ANSELC = ANSELD = ANSELE = ANSELG = 0x0000;

ANSELBbits.ANSB5 = 1; // Ensure AN5/RB5 is analog

/* Initialize and enable ADC module */

AD1CON1 = 0x0004;

AD1CON2 = 0x0000;

AD1CON3 = 0x000F;

AD1CON4 = 0x0000;

AD1CHS0 = 0x0005;

AD1CHS123 = 0x0000;

AD1CSSH = 0x0000;

AD1CSSL = 0x0000;

AD1CON1bits.ADON = 1;

Delay_us(20);

}

void Delay_us(unsigned int delay)

{

for (i = 0; i < delay; i++)

{

__asm__ volatile ("repeat #39");

__asm__ volatile ("nop");

}

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

16.3.5 Automatic Sample and Automatic Conversion Sequence

16.3.5.1 CLOCKED CONVERSION TRIGGER

The auto-conversion method provides a more automated process to sample and convert the

analog inputs, as shown in Figure 16-6. The sampling period is self-timed and the conversion

starts automatically upon termination of a self-timed sampling period. The Auto-Sample Time bits

(SAMC<4:0>) in the ADxCON3 register (ADxCON3<12:8>) select 0 to 31 ADC clock cycles (TAD)

for the sampling period. Refer to the “Electrical Characteristics” chapter of the specific device

data sheet for a minimum recommended sampling time (SAMCx bits value).

The SSRCG bit is set to ‘0’ and the SSRC<2:0> bits are set to ‘111’ to choose the internal

counter as the sample clock source, which ends sampling and starts conversion.

Figure 16-6: Automatic Sample and Automatic Conversion Sequence

Sample Time Conversion Time

SAMP

Sample Time

3 4

Conversion

Note 1: Sampling starts automatically after conversion.

2: Conversion starts automatically upon termination of self-timed sampling period.

3: Sampling starts automatically after conversion.

4: Conversion starts automatically upon termination of self-timed sampling period.

N • TAD

Conversion

–

N • TAD

dsPIC33E/PIC24E Family Reference Manual

16.3.5.2 EXTERNAL CONVERSION TRIGGER

In an Automatic Sample and Triggered Conversion Sequence, sampling starts automatically

after conversion and the conversion starts upon a trigger event from the selected peripheral, as

shown in Figure 16-7. This enables ADC conversion to be synchronized with the internal or

external events. The external conversion trigger is selected by configuring the SSRC<2:0> bits

as shown in Table 16-2. Refer to Section 16.4.8 “Conversion Trigger Sources” for various

external conversion trigger sources.

The ASAM bit must not be modified while the ADC is turned on. If automatic sampling is desired,

the ASAM bit must be set before turning the module on. The ADC module takes some amount

of time to stabilize (see the TDPU parameter in the specific device data sheet). If automatic

sampling is enabled, there is no assurance that the initial ADC results are correct until the ADC

module stabilizes. It may be necessary to discard the first few ADC results depending on the

Analog-to-Digital clock speed.

Figure 16-7: Automatic Sample and Triggered Conversion Sequence

Sample Time Conversion Time

SAMP

1 2

Sample Time

Conversion

Note 1: Sampling starts automatically after conversion.

2: Conversion starts upon trigger event.

3: Sampling starts automatically after conversion.

4: Conversion starts upon trigger event.

Conversion

SOC Trigger

–

dsPIC33E/PIC24E Family Reference Manual

For simultaneous sampling, the total time taken to sample and convert the channels is shown in

Equation 16-4.

Equation 16-4: Channel Sample and Conversion Total Time, Simultaneous Sampling

Selected

Figure 16-10: 4-Channel Simultaneous Sampling

Figure 16-11 and Figure 16-12 illustrate that, by default, multiple channels are sampled and

converted sequentially.

For sequential sampling, the total time taken to sample and convert channels is shown in

Equation 16-5.

Equation 16-5: Channel Sample and Conversion Total Time, Sequential Sampling Selected

Where:

TSIM = Total Time to Sample and Convert multiple channels with simultaneous sampling

SMP = Sampling Time (see Equation 16-1)

CONV = Conversion Time (see Equation 16-2)

M = Number of Channels selected by the CHPS<1:0> bits

TSIM = TSMP + (M • TCONV)

Sample 1

CH0

CH1

Sample 1

CH2

CH3

Convert 1

SOC

Trigger

Convert 1

Sample 2

Convert 2

Sample/Convert Sequence 1 Sample/Convert Sequence 2

4 73 5 6

Note 1: CH0-CH3 input multiplexer selects the analog input for sampling. The selected analog input connects to the

sample capacitor.

2: On a SOC trigger, CH0-CH3 sample capacitor disconnects from the multiplexer to simultaneously sample the

analog inputs. The analog value captured in CH0 is converted to equivalent digital bits.

3: The analog voltage captured in CH1 is converted to equivalent digital bits.

4: The analog voltage captured in CH2 is converted to equivalent digital bits.

5: The analog voltage captured in CH3 is converted to equivalent digital bits.

6: CH0-CH3 input multiplexer selects the next analog input for sampling. The selected analog input connects to

the sample capacitor.

7: On a SOC trigger, CH0-CH3 sample capacitor disconnects from the multiplexer to simultaneously sample the

analog inputs. The analog value captured in CH0 is converted to equivalent digital bits.

TSIM TSIM

1 2

Where:

TSEQ = Total Time to Sample and Convert multiple channels with sequential sampling

TCONV = Conversion Time (see Equation 16-2)

TSMP = Sampling Time (see Equation 16-1)

M = Number of Channels selected by the CHPS<1:0> bits

When TSMP < TCONV,

TSEQ = M • TCONV

TSEQ = TSMP + TCONV

(if M > 1)

(if M = 1)

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

Figure 16-11: 2-Channel Sequential Sampling (ASAM = )1

Figure 16-12: 4-Channel Sequential Sampling

Sample 1

CH0

CH1

Convert 1

SOC

Trigger

Sample 2

Convert 2

Sample/Convert Sequence 1 Sample/Convert Sequence 2

Sample 2 Sample 3

1 2 4

Note 1: CH0-CH1 input multiplexer selects the analog input for sampling. The selected analog input connects to

the sample capacitor.

2: On a SOC trigger, CH0 sample capacitor disconnects from the multiplexer to hold the input voltage

constant during conversion. The analog value captured in CH0 is converted to equivalent digital bits.

3: The CH0 multiplexer output connects to the sample capacitor after conversion. CH1 sample capacitor

disconnects from the multiplexer to hold the input voltage constant during conversion. The analog value

captured in CH1 is converted to equivalent digital bits.

4: The CH1 multiplexer output connects to the sample capacitor after conversion. CH0-CH1 input multiplexer

selects the next analog input for sampling.

5: On a SOC trigger, CH0 sample capacitor disconnects from the multiplexer to hold the input voltage

constant during conversion. The analog value captured in CH0 is converted to equivalent digital bits.

Sample 1

CH0

CH1

CH2

CH3

Convert 1

SOC

Trigger

Sample 1

Convert 2

Convert 2Sample 2

Sample 2

Sample/Convert Sequence 1 Sample/Convert Sequence 2

Sample 2

Sample 3

12473 56

Note 1: CH0-CH3 input multiplexer selects the analog input for sampling. The selected analog input connects to the

sample capacitor.

2: On a SOC trigger, CH0 sample capacitor disconnects from the multiplexer to hold the input voltage constant

during conversion. The analog value captured in CH0 is converted to equivalent digital bits.

3: The CH0 multiplexer output connects to the sample capacitor after conversion. CH1 sample capacitor 

disconnects from the multiplexer to hold the input voltage constant during conversion. The analog value 

captured in CH1 is converted to equivalent digital bits.

4: The CH1 multiplexer output connects to the sample capacitor after conversion. CH2 sample capacitor 

disconnects from the multiplexer to hold the input voltage constant during conversion. The analog value 

captured in CH2 is converted to equivalent digital bits.

5: The CH2 multiplexer output connects to the sample capacitor after conversion. CH3 sample capacitor 

disconnects from the multiplexer to hold the input voltage constant during conversion. The analog value 

captured in CH3 is converted to equivalent digital bits.

6: The CH3 multiplexer output connects to the sample capacitor after conversion. CH0-CH3 input multiplexer

selects the next analog input for sampling.

7: On a SOC trigger, CH0 sample capacitor disconnects from the multiplexer to hold the input voltage constant

during conversion. The analog value captured in CH0 is converted to equivalent digital bits.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

16.4.4 Voltage Reference Selection

The voltage references for Analog-to-Digital conversions are selected using the Voltage

Reference Configuration bits (VCFG<2:0>) in the ADCx Control Register 2 (ADxCON2<15:13>).

Table 16-6 lists the voltage reference selection for different bit settings.The Voltage Reference

High (VREFH) and the Voltage Reference Low (VREFL) to the ADC module can be supplied from

the internal AVDD and AVSS voltage rails or the external VREF+ and VREF- input pins. The external

voltage reference pins can be shared with the AN0 and AN1 inputs on low pin count devices. The

ADC module can still perform conversions on these pins when they are shared with the VREF+

and VREF- input pins. The voltages applied to the external reference pins must meet certain

specifications. For more details, refer to the “Electrical Characteristics” chapter of the specific

device data sheet.

Table 16-6: Voltage Reference Selection

16.4.5 ADC Clock Selection

The ADC module can be clocked from the instruction cycle clock (TCY) or by using the dedicated

internal RC clock (see Figure 16-13). When using the instruction cycle clock, a clock divider

drives the instruction cycle clock and enables a lower frequency to be chosen. The clock divider

is controlled by the ADC Conversion Clock Select bits (ADCS<7:0>) in the ADCx Control

Equation 16-6 shows the ADC clock period (TAD) as a function of the ADCSx control bits and the

device instruction cycle clock period, TCY.

Equation 16-6: ADC Clock Period

VCFG<2:0> VREFH VREFL

000 AVDD AVSS

001 VREF+ AVSS

010 AVDD VREF-

011 VREF+ VREF-

1xx AVDD AVSS

Note: Refer to the “Electrical Characteristics” chapter in the specific device data sheet

for minimum TAD specifications.

If ADRC = 0:

ADC Clock Period (TAD) = TCY • (ADCS<7:0> + 1)

If ADRC = 1:

ADC Clock Period (TAD ADRC) = T

dsPIC33E/PIC24E Family Reference Manual

The ADC module has a dedicated internal RC clock source that can be used to perform

conversions. The internal RC clock source is used when Analog-to-Digital conversions are

performed while the device is in Sleep mode. The internal RC oscillator is selected by setting the

ADC Conversion Clock Source bit (ADRC) in ADCx Control Register 3 (ADxCON3<15>). When

the ADRC bit is set, the ADCS<7:0> bits have no effect on the ADC operation.

Figure 16-13: ADC Clock Generation

16.4.6 Output Data Format Selection

Figure 16-14 illustrates that the ADC result is available in four different numerical formats. The

Data Output Format bits (FORM<1:0>) in the ADCx Control Register 1 (ADxCON1<9:8>) select

the output data format. Table 16-7 lists the ADC output format for different bit settings.

Table 16-7: Voltage Reference Selection

Note: Refer to the “Electrical Characteristics” chapter in the specific device data sheet

for ADRC frequency specifications.

FORM<1:0> Data Information Selection

11 Signed Fractional Format

10 Unsigned Fractional Format

01 Signed Integer Format

00 Unsigned Integer Format

ADCS<7:0>

ADRC

ADC Clock (TAD)

TP(1)

Note 1: T .P = 1/FP

2: Refer to the “Electrical Characteristics” chapter in the specific device data sheet

for the exact ADC internal RC value.

ADC Conversion Clock

Multiplier 1, 2, 3, 4, 5, ..., 256

ADC Internal RC(2)

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

Figure 16-14: ADC Output Format

0000 0000 0000 0000 (0)

0000 0011 1111 1111 (1023)

0000 0010 0000 0000

(512)

1111 1110 0000 0000 (-512)

0000 0001 1111 1111 (511)

0000 0000 0000 0000 (0)

0000 0011 1111 1111 (4095)

0000 0010 0000 0000 (2048)

1111 1000 0000 0010 (-2046)

0000 0111 1111 1101 (2045)

0000 0000 0000 0000 (0)

10-Bit ADC 12-Bit ADC

FORM = 0b00

Unsigned

Integer

FORM = 0b01

Signed

Integer

0000 0000 0000 0000 (0)

1111 1111 1100 0000 (+0.999)

1000 0000 0000 0000 (0.5)

1000 0000 0000 0000 (-1)

0111 1111 1100 0000 (+0.999)

0000 0000 0000 0000 (0)

VREFH

VREFL

0000 0000 0000 0000 (0)

FORM = 0b10

Unsigned

Fraction (Q16)

FORM = 0b11

Signed

Fraction(Q15)

Input

0111 1111 1111 0000 (+0.999)

1000 0000 0000 0000 (-1)

VREFH

VREFL

1000 0000 0000 0000 (0.5)

Input

0000 0000 0000 0000 (0)

1111 1111 1111 0000 (+0.999)

VREFH

VREFL Input

VREFH

VREFL Input

VREFH

VREFL Input

VREFH

VREFL Input

VREFH

VREFL Input

VREFH

VREFL Input

Produkt Specifikationer

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