Microchip PIC24FJ192GB108 Manual

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 2007-2015 Microchip Technology Inc. DS70000195G-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 I

C Bus Characteristics..................................................................................................... 4

3.0 Control and Status Registers ............................................................................................ 8

4.0 Enabling I

C Operation ................................................................................................... 18

5.0 Communicating as a Master in a Single Master Environment ........................................ 20

6.0 Communicating as a Master in a Multi-Master Environment .......................................... 34

7.0 Communicating as a Slave ............................................................................................. 37

8.0 Connection Considerations for I

C Bus .......................................................................... 61

9.0 Operation in Power-Saving Modes ................................................................................. 63

10.0 Peripheral Module Disable (PMDx) Registers ................................................................ 63

11.0 Effects of a Reset............................................................................................................ 63

12.0 Constant-Current Source ................................................................................................ 64

13.0 Register Maps................................................................................................................. 66

14.0 Design Tips ..................................................................................................................... 67

15.0 Related Application Notes............................................................................................... 68

16.0 Revision History .............................................................................................................. 69

Inter-Integrated Circuit (I2C)

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 2  2007-2015 Microchip Technology Inc.

This document supersedes the following PIC24 and dsPIC

DSC Family Reference Manual sections:

1.0 INTRODUCTION

The Inter-Integrated Circuit (I

C) module is a serial interface useful for communicating with other

peripheral or microcontroller (MCU) devices. The external peripheral devices may be serial

EEPROMs, display drivers, Analog-to-Digital Converters (ADC) and so on.

The I

C module can operate as any one of the following in the I

C system:

• Slave device

• Master device in a single master system (slave may be active)

• Master or slave device in a multi-master system (bus collision detection and arbitration are

available)

The I

C module contains an independent I

C master logic and a I

C slave logic, which generates

interrupts based on their events. In the multi-master systems, the user software is simply

partitioned into the master controller and the slave controller.

When the I

C master logic is active, the slave logic also remains active, detecting the state of the

bus and potentially receiving messages from itself in a single master system or from the other

masters in a multi-master system. No messages are lost during the multi-master bus arbitration.

In a multi-master system, the bus collision conflicts with the other masters in the system when

detected, and the module provides a method to terminate and then restart the message.

The I

C module contains a Baud Rate Generator (BRG). The I

C BRG does not consume other

timer resources in the device. Figure 1-1 illustrates the I

C module block diagram.

Key features of the I

C module include the following:

• Independent master and slave logic

• Multi-master support which prevents message losses in arbitration

• Detects 7-bit and 10-bit device addresses with configurable address masking in Slave mode

• Detects general call addresses as defined in the I

C protocol

• Bus Repeater mode, allowing the module to accept all messages as a slave, irrespective of

the address

• Automatic SCLx clock stretching provides delays for the processor to respond to a slave

data request

• Supports 100 kHz and 400 kHz bus specifications

• Supports the Intelligent Platform Management Interface (IPMI) standard

• Supports SDAx hold time for SMBus (300 nS or 150 nS) in Slave mode

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC24 and dsPIC33 devices.

Please consult the note at the beginning of the “Inter-Integrated Circuit (I

C)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at:

http://www.microchip.com

DS Number Section Number Title

DS70195 19 dsPIC33F/PIC24H Family Reference Manual

DS70330 19 dsPIC33E/PIC24E Family Reference Manual

DS39702 24 PIC24F Family Reference Manual

DS70235 19 PIC24H Family Reference Manual

DS70068 21 dsPIC30F Family Reference Manual

Note:

For more information, refer to the SDAHT bit description in the specific device data sheet.

 2007-2015 Microchip Technology Inc. DS70000195G-page 3

Inter-Integrated Circuit (I

Figure 1-1: I

C Block Diagram

I2CxRCV

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

Clock

Address Match

Clock

Stretching

I2CxTRN

LSB

Shift Clock

BRG

Reload

Control

or T

(1)

Acknowledge

Generation

I2CxCONH

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Down Counter

I2CxCONL

Write

Read

Note 1: Refer to the specific device data sheet for the clock rate.

I2CxADD

Start and Stop

Bit Detect

Start and Stop

Bit Generation

Collision

Detect

I2CxMSK

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 4  2007-2015 Microchip Technology Inc.

2.0 I2C BUS CHARACTERISTICS

The I

C bus is a 2-wire serial interface. Figure 2-1 illustrates the schematic of an I

C connection

between a dsPIC33/PIC24 device and a 24LC256 I

C serial EEPROM, which is a typical

example for any I

C interface.

The I

C interface uses a comprehensive protocol to ensure reliable transmission and reception

of the data. When communicating, one device acts as the “master” and it initiates transfer on the

bus, and generates the clock signals to permit that transfer, while the other devices act as the

“slave” responding to the transfer. The clock line, SCLx, is output from the master and input to

the slave, although occasionally the slave drives the SCLx line. The data line, SDAx, may be

output and input from both the master and slave.

Because the SDAx and SCLx lines are bidirectional, the output stages of the devices driving the

SDAx and SCLx lines must have an open-drain in order to perform the wired-AND function of the bus.

External pull-up resistors are used to ensure a high level when no device is pulling the line down.

In the I

C interface protocol, each device has an address. When a master needs to initiate a data

transfer, it first transmits the address of the device that it wants to “communicate”. All of the

devices “listen” to see if this is their address. Within this address, bit 0 specifies whether the

master wants to read from or write to the slave device. The master and slave are always in

opposite modes (Transmitter or Receiver) of operation during a data transfer. That is, they

operate in either of the following two relationships:

• Master-Transmitter and Slave-Receiver

• Slave-Transmitter and Master-Receiver

In both cases, the master originates the SCLx clock signal.

Figure 2-1: Typical I

C Interconnection Block Diagram

Note:

SCLx and SDAx must be configured as digital.

SCLx

SDAx

dsPIC33/PIC24

SDA

SCL

2.2 k24LC256

(typical)

 2007-2015 Microchip Technology Inc. DS70000195G-page 5

Inter-Integrated Circuit (I

2.1 Bus Protocol

The following I

C bus protocol has been defined:

• The data transfer may be initiated only when the bus is not busy.

• During the data transfer, the data line must remain stable whenever the SCLx clock line is

high. Any changes in the data line, while the SCLx clock line is high, will be interpreted as a

Start or Stop condition.

Accordingly, the bus conditions are defined as illustrated in Figure 2-2.

Figure 2-2: I

C Bus Protocol States

2.1.1 START DATA TRANSFER (S)

After a bus Idle state, a high-to-low transition of the SDAx line while the clock (SCLx) is high

determines a Start condition. All data transfers must be preceded by a Start condition.

2.1.2 STOP DATA TRANSFER (P)

A low-to-high transition of the SDAx line while the clock (SCLx) is high determines a Stop

condition. All data transfers must end with a Stop condition.

2.1.3 REPEATED START (R)

After a Wait state, a high-to-low transition of the SDAx line while the clock (SCLx) is high

determines a Repeated Start condition. Repeated Starts allow a master to change bus direction

or address a slave device without relinquishing control of the bus.

2.1.4 DATA VALID (D)

After a Start condition, the state of the SDAx line represents valid data when the SDAx line is

stable for the duration of the high period of the clock signal. There is one bit of data per SCLx

clock.

2.1.5 ACKNOWLEDGE (A) OR NOT ACKNOWLEDGE (N)

All data byte transmissions must be Acknowledged (ACK) or Not Acknowledged (NACK) by the

receiver. The receiver will pull the SDAx line low for an ACK or release the SDAx line for a NACK.

The Acknowledge is a 1-bit period using one SCLx clock.

2.1.6 WAIT/DATA INVALID (Q)

The data on the line must be changed during the low period of the clock signal. The devices may

also stretch the clock low time by asserting a low on the SCLx line, causing a Wait on the bus.

2.1.7 BUS IDLE (I)

Both data and clock lines remain high after a Stop condition and before a Start condition.

Address

Valid

Data

Allowed

to Change

Stop

Condition

Start

Condition

SCLx

SDAx

(I) (S) (D) (A) or (N) (P) (I)

Data or

(Q)

ACK/NACK

Valid

NACK

ACK

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 6  2007-2015 Microchip Technology Inc.

2.2 Message Protocol

A typical I

C message is illustrated in Figure 2-3. In this example, the message will read a

specified byte from a 24LC256 I

C serial EEPROM. The dsPIC33/PIC24 device will act as the

master and the 24LC256 device will act as the slave.

Figure 2-3 illustrates the data as driven by the master device and the slave device, taking into

account that the combined SDAx line is a wired-AND of the master and slave data. The master

device controls and sequences the protocol. The slave device will only drive the bus at

specifically determined times.

Figure 2-3: A Typical I

C Message: Read of Serial EEPROM (Random Address Mode)

2.2.1 START MESSAGE

Each message is initiated with a Start condition and terminated with a Stop condition. The

number of data bytes transferred between the Start and Stop conditions is determined by the

master device. As defined by the system protocol, the bytes of the message may have special

meaning, such as the device address byte or the data byte.

2.2.2 ADDRESS SLAVE

In Figure 2-3, the first byte is the device address byte, which must be the first part of any I

message. It contains a device address and a R/W status bit. Note that R/W = 0 for this first

address byte, indicating that the master will be a transmitter and the slave will be a receiver.

2.2.3 SLAVE ACKNOWLEDGE

The receiving device is obliged to generate an Acknowledge signal, ACK, after the reception of

each byte. The master device must generate an extra SCLx clock, which is associated with this

Acknowledge bit.

2.2.4 MASTER TRANSMIT

The next two bytes, sent by the master to the slave, are data bytes that contain the location of

the requested EEPROM data byte. The slave must Acknowledge each of the data bytes.

2.2.5 REPEATED START

The slave EEPROM has the required address information that is required to return the requested

data byte to the master. However, the R/W status bit from the first device address byte specifies

the master transmission and the slave reception. The direction of the bus must be reversed for

the slave to send data to the master.

To perform this function without ending the message, the master sends a Repeated Start. The

Repeated Start is followed with a device address byte containing the same device address as

before, and with R/W = 1, to indicate the slave transmission and the master reception.

Bus

Master

SDAx

Start

Address

Byte

EEPROM Address

High Byte

EEPROM Address

Low Byte Address

Byte Data

Byte

S1 0 1 0 AAA0

210 R1 0 1 0 AAA1

210 P

Slave

SDAx

Activity

AAAA

Output

Idle

R/W

ACK

Restart

ACK

NACK

Stop

Idle

R/W

 2007-2015 Microchip Technology Inc. DS70000195G-page 7

Inter-Integrated Circuit (I

2.2.6 SLAVE REPLY

The slave transmits the data byte by driving the SDAx line, while the master continues to

originate clocks but releases its SDAx drive.

2.2.7 MASTER ACKNOWLEDGE

During reads, a master must terminate data requests to the slave by generating a NACK on the

last byte of the message.

2.2.8 STOP MESSAGE

The master sends a Stop signal to terminate the message and returns the bus to an Idle state.

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 8  2007-2015 Microchip Technology Inc.

3.0 CONTROL AND STATUS REGISTERS

The I

C module has registers for operation that are accessible by the user application. All

registers are accessible in either Byte or Word mode. The registers are as follows:

•

I2CxCON: I2Cx Control Register

I2CxCONL: I2Cx Control Register Low

and

I2CxCONH: I2Cx Control Register High

These registers allow control of the module’s operation.

•

I2CxSTAT: I2Cx Status Register

This register contains status flags indicating the module’s state during operation.

•

I2CxMSK: I2Cx Slave Mode Address Mask Register

This register designates which bit positions in the I2CxADD register can be ignored, which

allows for multiple address support.

•

ISRCCON: I2Cx Current Source Control Register

(1)

This register allows control of the current source module.

•

I2CxRCV: I2Cx Receive Buffer Register

This is the buffer register from which data bytes can be read. The I2CxRCV register is a

read-only register.

•

I2CxTRN: I2Cx Transmit Register

This is the transmit register. The bytes are written to this register during a transmit operation.

The I2CxTRN register is a read/write register.

• I2CxADD: I2Cx Address Register

This register holds the slave device address.

• I2CxBRG: I2Cx Baud Rate Generator Reload Register

This register holds the BRG reload value for the I

C module BRG.

The transmit data is written to the I2CxTRN register. This register is used when the module

operates as a master transmitting data to the slave or when it operates as a slave sending reply

data to the master. As the message progresses, the I2CxTRN register shifts out the individual

bits. Therefore, the I2CxTRN register cannot be written to unless the bus is Idle.

The data being received by either the master or the slave is shifted into a non-accessible shift

In receive operations, the I2CxRSR and I2CxRCV registers create a double-buffered receiver.

This allows reception of the next byte to begin before reading the current byte of the received

data.

If the module receives another complete byte before the user software reads the previous byte

from the I2CxRCV register, a receiver overflow occurs and sets the I2COV bit (I2CxSTAT<6>).

The byte in the I2CxRSR register is lost if BOEN = 0. Further reception and clock stretching are

disabled until the I

C module sees a Start/Repeated, Start/Stop condition on the bus. If the

I2COV flag has been cleared, the reception can proceed normally. If the I2COV flag is not

cleared, the module will receive the next byte correctly, but will send a NACK. It will then be

unable to receive further bytes or stretch the clock until it detects a Start/Repeated and Start/Stop

condition.

The I2CxADD register holds the slave device address. In 10-Bit Addressing mode, all bits are

relevant. In 7-Bit Addressing mode, only the I2CxADD<6:0> bits are relevant. The

I2CxADD<6:0> bits correspond to the upper 7 bits in the address byte. The Read/Write bit (R/W)

is not included in the value in this register. The A10M bit (I2CxCON<10> or I2CxCONL<10>)

specifies the expected mode of the slave address. By using the I2CxMSK register with the

I2CxADD register in Slave Addressing mode, one or more bit positions can be removed from the

exact address matching, allowing the module, in Slave mode, to respond to multiple addresses.

Note 1:

The I2CxCONL, I2CxCONH and ISRCCON registers are not available on all

devices. Refer to the specific device data sheet for availability.

 2007-2015 Microchip Technology Inc. DS70000195G-page 9

Inter-Integrated Circuit (I

R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL IPMIEN

( )1

A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15

I2CEN:

I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0 = Disables the I2Cx module; all the I

C pins are controlled by port functions

bit 14

Unimplemented:

Read as ‘0’

bit 13

I2CSIDL:

I2Cx Stop in Idle Mode bit

1 = Discontinues the module operation when a device enters the Idle mode

0 = Continues the module operation in the Idle mode

bit 12

SCLREL:

SCLx Release Control bit (when operating as I

C slave)

1 = Releases the SCLx clock

0 = Holds the SCLx clock low (clock stretch)

If STREN = 1:

User software may write ‘0’ to initiate a clock stretch and write ‘1’ to release the clock. Hardware clears

at the beginning of every slave data byte transmission. Hardware clears at the end of every slave

address byte reception. Hardware clears at the end of every slave data byte reception.

If STREN = 0:

User software may only write ‘1’ to release the clock. Hardware clears at the beginning of every slave

data byte transmission. Hardware clears at the end of every slave address byte reception.

bit 11

IPMIEN:

IPMI Enable bit

( )1

1 = IPMI Support mode is enabled, all addresses are Acknowledged

0 = IPMI Support mode is disabled

bit 10

A10M:

10-Bit Slave Address bit

1 = I2CxADD register is a 10-bit slave address

0 = I2CxADD register is a 7-bit slave address

bit 9

DISSLW:

Disable Slew Rate Control bit

1 = Slew rate control is disabled

0 = Slew rate control is enabled

bit 8

SMEN:

SMBus Input Levels bit

1 = Enables the I/O pin thresholds compliant with the SMBus specification

0 = Disables the SMBus input thresholds

bit 7

GCEN:

General Call Enable bit (when operating as I

C slave)

1 = Enables the interrupt when a general call address is received in the I2CxRSR register (module is

enabled for reception)

0 = Disables the general call address

bit 6

STREN:

SCLx Clock Stretch Enable bit (I

C Slave mode only; used in conjunction with the SCLREL bit)

1 = Enables the user software or the receive clock stretching

0 = Disables the user software or the receive clock stretching

Note 1:

The IPMIEN bit should not be set when the I

C module is operating as a master.

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 10  2007-2015 Microchip Technology Inc.

bit 5

ACKDT:

Acknowledge Data bit (I

C Master mode; receive operation only)

Value that will be transmitted when the user software initiates an Acknowledge sequence.

1 = Sends a NACK during an Acknowledge

0 = Sends an ACK during an Acknowledge

bit 4

ACKEN:

Acknowledge Sequence Enable bit (I

C Master mode receive operation)

1 = Initiates the Acknowledge sequence on the SDAx and SCLx pins and transmits the ACKDT data bit

(hardware clears at the end of the master Acknowledge sequence)

0 = Acknowledge sequence is not in progress

bit 3

RCEN:

Receive Enable bit (I

C Master mode)

1 = Enables Receive mode for I

C (hardware clears at the end of eighth bit of master receive data byte)

0 = Receive sequence is not in progress

bit 2

PEN:

Stop Condition Enable bit (I

C Master mode)

1 = Initiates the Stop condition on the SDAx and SCLx pins (hardware clears at the end of master Stop

sequence)

0 = Stop condition is not in progress

bit 1

RSEN:

Repeated Start Condition Enable bit (I

C Master mode)

1 = Initiates the Repeated Start condition on the SDAx and SCLx pins (hardware clears at the end of

master Repeated Start sequence)

0 = Repeated Start condition is not in progress

bit 0

SEN:

Start Condition Enable bit (I

C Master mode)

1 = Initiates the Start condition on the SDAx and SCLx pins (hardware clears at the end of master Start

sequence)

0 = Start condition is not in progress

Note 1:

The IPMIEN bit should not be set when the I

C module is operating as a master.

 2007-2015 Microchip Technology Inc. DS70000195G-page 13

Inter-Integrated Circuit (I

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

Unimplemented:

Read as ‘0’

bit 6

PCIE:

Stop Condition Interrupt Enable bit (I

C Slave mode only)

1 = Enables the interrupt on detection of a Stop condition

0 = Stop detection interrupts are disabled

bit 5

SCIE:

Start Condition Interrupt Enable bit (I

C Slave mode only)

1 = Enables the interrupt on detection of a Start or Restart condition

0 = Start detection interrupts are disabled

bit 4

BOEN:

Buffer Overwrite Enable bit (I

C Slave mode only)

1 = The I2CxRCV register is updated and an ACK is generated for a received address or data byte,

ignoring the state of the I2COV bit only if the RBF bit = 0

0 = The I2CxRCV register is only updated when the I2COV bit is clear

bit 3

SDAHT:

SDAx Hold Time Selection bit

( )1

1 = Minimum of 300 ns hold time on SDAx after the falling edge of the SCLx clock

0 = Minimum of 100 ns hold time on SDAx after the falling edge the of SCLx clock

bit 2

SBCDE:

Slave Mode Bus Collision Detect Enable bit (I

C Slave mode only)

If, on the rising edge of the SCLx, SDAx is sampled low when the module is outputting a high state, the

BCL bit is set and the bus goes into Idle mode. This Detection mode is valid only during the data and

ACK transmit sequences.

1 = Enables the slave bus collision interrupts

0 = Disables the slave bus collision interrupts

bit 1

AHEN:

Address Hold Enable bit (I

C Slave mode only)

1 = Following the falling edge of the eighth SCLx clock for a matching received address byte; the

SCLREL bit (I2CxCONL<12>) will be cleared and the SCLx will be held low

0 = Address holding is disabled

bit 0

DHEN:

Data Hold Enable bit (I

C Slave mode only)

1 = Following the eighth falling edge of the SCLx clock for a received data byte; slave hardware clears

the SCLREL bit (I2CxCONL<12>) and SCLx is held low

0 = Data holding is disabled

Note 1:

This bit must be set to ‘0’ for 1 MHz operation.

Produkt Specifikationer

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Model:	PIC24FJ192GB108

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