Microchip PIC24FJ256DA206 Manual

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© 2009 Microchip Technology Inc. DS39731A-page 43-1
Graphics Controller
Module (GFX)
43
Section 43. Graphics Controller Module (GFX)
HIGHLIGHTS
This section of the manual contains the following topics:
43.1 Introduction .................................................................................................................. 43-2
43.2 Module Registers ......................................................................................................... 43-4
43.3 Operation ................................................................................................................... 43-27
43.4 Display Controller....................................................................................................... 43-34
43.5 Graphical Processing Units (GPUs)........................................................................... 43-49
43.6 Interrupts.................................................................................................................... 43-65
43.7 Display Power Sequencing ........................................................................................ 43-67
43.8 Operation in Power-Saving Modes ............................................................................ 43-68
43.9 Effects of a Reset.......................................................................................................43-69
43.10 Display Interface Timing............................................................................................. 43-70
43.11 Register Map.............................................................................................................. 43-74
43.12 Related Application Notes.......................................................................................... 43-75
43.13 Revision History ......................................................................................................... 43-76
PIC24F Family Reference Manual
DS39731A-page 43-2 © 2009 Microchip Technology Inc.
43.1 INTRODUCTION
The Graphics Controller (GFX) module is specifically designed to directly interface with display
glasses, with built-in analog drive, to individually control pixels in the screen. The module also pro-
vides accelerated rendering of vertical and horizontal lines, rectangles, copying of a rectangular
area between different locations on the screen, drawing texts and decompressing compressed
data. The use of the accelerated rendering is performed using command FIFO. Once initiated, the
hardware will perform the rendering freeing up the CPU for other tasks. Software can either poll the
status or use interrupts to continue rendering succeeding shapes.
43.1.1 GFX Module Features
The GFX module supports three categories of display glasses:
• Monochrome STN
• Color STN
• Color TFT
Programmable vertical and horizontal synchronization signals’ timing is provided to meet the
display’s timing requirements.
The GFX module includes the following features:
• Graphics Hardware Accelerators:
- Character Graphics Processing Unit (CHRGPU)
- Rectangle Copy Graphics Processing Unit (RCCGPU)
- Inflate Processing Unit (IPU)
• 256 Color Look-up Table (CLUT) Entries
• Supports 1/2/4/8/16 bits-per-pixel (bpp) Color Depth
• Programmable Display Resolution
• Supports the following Display Interfaces:
- 4/8/16-Bit Monochrome STN
- 4/8/16-Bit Color STN
- 9/12/18/24-Bit Color TFT (18 and 24-bit displays are connected as 16-bit 5-6-5 RGB
color format)
Figure 43-1 illustrates the GFX module pinout and image buffer sources. In some devices,
system RAM can also reside externally to the device. Refer to the applicable device data sheet
for details.
© 2009 Microchip Technology Inc. DS39731A-page 43-3
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Figure 43-1: Graphics Module Pinout and Block Diagram
PIC24F Graphics
Controller Module
To Display
Glass
System
RAM
VSYNC
GCLK
GEN
GPWR
HSYNC
GD<15:0>
GPU Command
Interface
Registers
and Control
Interface
CHRGPURCCGPU IPU
Memory Request Arbiter
Display Module
Interface
CLUT
Graphics
Controller Clock
(G1CLK)
Display Interface
Clock (DISPCLK)
System Clock
PIC24F Family Reference Manual
DS39731A-page 43-4 © 2009 Microchip Technology Inc.
43.2 MODULE REGISTERS
The GFX module includes the following control and status registers:
• G1CMDL and G1CMDH – GPU Command Low/High Register (Register 43-1 and
Register 43-2)
These registers form the 32-bit command field. Commands written to these registers are
loaded to the command FIFO.
• G1CON1 – Display Control Register 1 (Register 43-3)
This register controls the enabling of the GFX module, sets the watermark level that
triggers the interrupt for a number of queued commands in the command FIFO and sets
up the color depth of the GPU operations in bits-per-pixel (bpp). This register also holds
the status of the current queued commands in the 16-deep command FIFO.
• G1CON2 – Display Control Register 2 (Register 43-4)
This register sets up the type of display glass hooked up to the module, the display color
depth in bits-per-pixel, the display data stagger control to reduce simultaneous switching
output noise and the type of test pattern that will be generated on the screen when in test
mode.
• G1CON3 – Display Control Register 3 (Register 43-5)
This register controls the display power signal, polarities and enabling of the display clock,
vertical and horizontal synchronization, and data enable signals.
• G1STAT – Status Register (Register 43-6)
This register contains the status of the GPUs, vertical/horizontal blanking, command
watermark level and command FIFO.
• G1IE – Interrupt Enable Register (Register 43-7)
This register contains the control bits to enable the different module’s interrupt sources that
go to the CPU.
• G1IR – Interrupt Status Register (Register 43-8)
This register contains the current status of the module’s interrupt sources.
• G1W1ADRL and G1W1ADRH – GPU Work Area 1 Start Address Register Low/High
(Register 43-9 and Register 43-10)
These registers define Work Area 1; they specifically define the start of the memory
address on which the GPU will operate. All GPUs use these two registers to define their
work areas.
• G1W2ADRL and G1W2ADRH – GPU Work Area 2 Start Address Register Low/High
(Register 43-11 and Register 43-12)
These registers define Work Area 2; they specifically define the start of the memory
address on which the GPU will operate. IPU and RCCGPU use these two registers to
define its 2nd work area.
• G1PUW – GPU Work Area Width Register (Register 43-13)
This register defines the GPU Work Areas 1 and 2 width in pixels.
• G1PUH – GPU Work Area Height Register (Register 43-14)
This register defines the GPU Work Areas 1 and 2 height in pixels.
• G1DPADRL and G1DPADRH – Display Buffer Start Address Register Low/High
(Register 43-15 and Register 43-16)
These registers define the start address of the display buffer.
• G1DPW – Display Buffer Width Register (Register 43-17)
This register defines the display buffer width in pixels.
• G1DPH – Display Buffer Height Register (Register 43-18)
This register defines the display buffer height in pixels.
• G1DPWT – Display Total Width Register (Register 43-19)
This register defines the total width of the display in pixels. This parameter may be greater
than the actual pixels displayed because of the vertical, non-display blanking requirement
in TFT displays.
© 2009 Microchip Technology Inc. DS39731A-page 43-5
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
• G1DPHT – Display Total Height Register (Register 43-20)
This register defines the total height of the display in pixels. This parameter may be greater
than the actual pixels displayed because of the horizontal, non-display blanking
requirement in TFT displays.
• G1ACTDA – Active Display Area Register (Register 43-21)
This register controls the number of lines before the first visible line is drawn and the
number of display clocks before the first visible pixel is drawn.
• G1HSYNC – Horizontal Synchronization Control Register (Register 43-22)
This register controls the horizontal synchronization pulse width and the start of the
synchronization signal.
• G1VSYNC – Vertical Synchronization Control Register (Register 43-23)
This register controls the vertical synchronization pulse width and the start of the
synchronization signal.
• G1DBLCON – Display Blanking Control Register (Register 43-24)
This register controls the number of lines between the start of the vertical blanking and the
first displayed line, and the number of display clock cycles before data enable that
indicates the first valid data for each line.
• G1CLUT – Color Look-up Table Control Register (Register 43-25)
This register enables the CLUT usage, CLUT read/write enable bit, CLUT read trigger bit
and the address of the CLUT entry that will be read or modified. This register also contains
the CLUT read/write busy bit.
• G1CLUTWR – CLUT Memory Write Data Register (Register 43-26)
This register specifies the data written to the CLUT memory with the address specified in
the G1CLUT register.
• G1CLUTRD – CLUT Memory Read Data Register (Register 43-27)
This register specifies the data read from the CLUT memory with the address specified in
the G1CLUT register.
• G1MRGN – Interrupt Advance Register (Register 43-28)
This register specifies the number of vertical and horizontal blanking bits that will trigger in
advance the interrupts for the vertical and horizontal blanking signals.
• G1CHRX and G1CHRY – Character X and Y Coordinate Print Position Register
(Register 43-29 and Register 43-30)
These registers specify the X and Y coordinate position of the character to be rendered in
the image buffer by the CHRGPU.
• G1IPU – Inflate Processor Status Register (Register 43-31)
This register contains the status bits associated with the inflate processor.
• G1DBEN – Data I/O Pad Enable Register (Register 43-32)
This register controls the enabling of the I/O pads to switch to the display controller.
PIC24F Family Reference Manual
DS39731A-page 43-6 © 2009 Microchip Technology Inc.
Register 43-1: G1CMDL: GPU Command Low Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCMD15 GCMD14 GCMD13 GCMD12 GCMD11 GCMD10 GCMD9 GCMD8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCMD7 GCMD6 GCMD5 GCMD4 GCMD3 GCMD2 GCMD1 GCMD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 GCMD<15:0>: Low GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register
will not trigger the loading of GCMD<31:0> to the command FIFO. For command FIFO loading, see the
G1CMDH register description.
Register 43-2: G1CMDH: GPU Command High Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCMD31 GCMD30 GCMD29 GCMD28 GCMD27 GCMD26 GCMD25 GCMD24
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCMD23 GCMD22 GCMD21 GCMD20 GCMD19 GCMD18 GCMD17 GCMD16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 GCMD<31:16>: High GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the
G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to G1CMDH
are allowed, but only a high byte write will trigger the command loading to the FIFO. Low byte write to
this register will only update the G1CMDH<7:0> bits.
© 2009 Microchip Technology Inc. DS39731A-page 43-7
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-3: G1CON1: Display Control Register 1
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
G1EN — G1SIDL GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0
PUBPP2 PUBPP1 PUBPP0 GCMDCNT4 GCMDCNT3 GCMDCNT2 GCMDCNT1 GCMDCNT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 G1EN: Module Enable bit
1 = Display module enabled
0 = Display module disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 G1SIDL: Stop in Idle bit
1 = Display module stops in Idle mode
0 = Display module does not stop in Idle mode
bit 12-8 GCMDWMK<4:0>: Command FIFO Watermark bits
Sets the command watermark level that triggers the CMDLVIF interrupt and sets the CMDLV flag.
GCMDWMK<4:0> > 10000 = Reserved:
10000 = If the number of commands present in the FIFO goes from 16 to 15 commands, the CMDLVIF
interrupt will trigger and the CMDLV flag will be set
01111 = If the number of commands present in the FIFO goes from 15 to 14 commands, the CMDLVIF
interrupt will trigger and the CMDLV flag will be set
•
•
•
00001 = If the number of commands present in the FIFO goes from 1 to 0 commands, the CMDLVIF
interrupt will trigger and the CMDLV flag will be set
00000 = The CMDLVIF interrupt will not trigger and the CMDLV flag will not be set
bit 7-5 PUBPP<2:0>: GPU bits-per-pixel Setting bits
Other = Reserved
100 = 16 bits-per-pixel
011 = 8 bits-per-pixel
010 = 4 bits-per-pixel
001 = 2 bits-per -pixel
000 = 1 bit-per-pixel
bit 4-0 GCMDCNT<4:0>: Command FIFO Occupancy Status bits
When FIFO is full, any additional commands written to the FIFO are discarded.
10000 = 16 commands present in the FIFO
01111 = 15 commands present in the FIFO
•
•
•
00001 = 1 command present in the FIFO
00000 = 0 commands present in the FIFO
PIC24F Family Reference Manual
DS39731A-page 43-8 © 2009 Microchip Technology Inc.
Register 43-4: G1CON2: Display Control Register 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0 — — DPTEST1 DPTEST0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
DPBPP2 DPBPP1 DPBPP0 — — DPMODE2 DPMODE1 DPMODE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 DPGWDTH<1:0>: STN Display Glass Data Width bits
11 = Reserved
10 = 16 bits wide
01 = 8 bits wide
00 = 4 bits wide
These bits have no effect on TFT mode. The TFT display glass data width is always assumed to be
16 bits wide.
bit 13-12 DPSTGER<1:0>: Display Data Timing Stagger bits
Refer to section 43.4.4 “Display Data Stagger” for details.
11 = Delays of the display data are staggered in groups:
Bit Group 0: 0 4 8 12 – not delayed
Bit Group 1: 1 5 9 13 – delayed by ½ GPUCLK cycle
Bit Group 2: 2 6 10 14 – delayed by full GPUCLK cycle
Bit Group 3: 3 7 11 15 – delayed by 1½ GPUCLK cycle
10 = Even bits of the display data are delayed by 1 full GPUCLK cycle; odd bits are not delayed
01 = Odd bits of the display data are delayed by ½ GPUCLK cycle; even bits are not delayed
00 = Display data timing is all synchronized on one GPUCLK edge
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8 DPTEST<1:0>: Display Test Pattern Generator bits
Test patterns can be used to test the interface to the display glass without the need to set up memory
interface and display buffer.
11 = Borders
10 = Bars
01 = Black screen
00 = Normal Display mode, test patterns are off
bit 7-5 DPBPP<2:0>: Display bits-per-pixel Setting bits
This setting must match the GPU bits-per-pixel set in the PUBPP<2:0> (G1CON1<7:5>) bits.
100 = 16 bits-per-pixel
011 = 8 bits-per-pixel
010 = 4 bits-per-pixel
001 = 2 bits-per-pixel
000 = 1 bit-per-pixel
Other = Reserved
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 DPMODE<2:0>: Display Glass Type bits
011 = Color STN type
010 = Mono STN type
001 = TFT type
000 = Display off
Other = Reserved
© 2009 Microchip Technology Inc. DS39731A-page 43-9
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-5: G1CON3: Display Control Register 3
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — DPPINOE DPPOWER
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPCLKPOL DPENPOL DPVSPOL DPHSPOL DPPWROE DPENOE DPVSOE DPHSOE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9 DPPINOE: Display Pin Output Pad Enable bit
DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE, DPPWROE,
DPVSOE and DPHSOE to enable the associated pads.
1 = Enable display output pads
0 = Disable display output pads
Pins used by the signals are assigned to the next enabled module that uses the same pins. For data
signals, GDBEN<15:0> can be used to disable or enable specific data signals while DPPINOE is set.
bit 8 DPPOWER: Display Power Sequencer Control bit
(Refer to Section 43.7 “Display Power Sequencing” for details)
1 = Set display power sequencer control port (GPWR) to ‘1’
0 = Set display power sequencer control port (GPWR) to ‘0’
bit 7 DPCLKPOL: Display Glass Clock (GCLK) Polarity bit
1 = Display latches data on positive edge of GCLK
0 = Display latches data on negative edge of GCLK
bit 6 DPENPOL: Display Enable Signal (GEN) Polarity bit
For TFT mode (DPMODE (G1CON2<2:0>) = 001):
1 = Active-high (GEN)
0 = Active-low (GEN)
For STN mode (DPMODE (G1CON2<2:0>) = 010 or 011):
1 = GEN connects to shift clock input of the display (Shift Clock mode)
0 = GEN connects to MOD input of the display (Line/Frame Toggle mode)
bit 5 DPVSPOL: Display Vertical Synchronization (VSYNC) Polarity bit
1 = Active-high (VSYNC)
0 = Active-low (VSYNC)
bit 4 DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit
1 = Active-high (HSYNC)
0 = Active-low (HSYNC)
bit 3 DPPWROE: Display Power Sequencer Control Port (GPWR) Enable bit
1 = GPWR port enabled (pin controlled by DPPOWER (G1CON3<8>) bit)
0 = GPWR port disabled (pin can be used as ordinary I/O)
bit 2 DPENOE: Display Enable Port Enable (GEN) bit
1 = GEN port enabled
0 = GEN port disabled
bit 1 DPVSOE: Display Vertical Synchronization Port Enable bit
1 = VSYNC port enabled
0 = VSYNC port disabled
bit 0 DPHSOE: Display Horizontal Synchronization Port Enable bit
1 = HSYNC port enabled
0 = HSYNC port disabled
PIC24F Family Reference Manual
DS39731A-page 43-10 © 2009 Microchip Technology Inc.
Register 43-6: G1STAT: STATUS Register
R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PUBUSY — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
IPUBUSY RCCBUSY CHRBUSY VMRGN HMRGN CMDLV CMDFUL CMDMPT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PUBUSY: Processing Units are Busy Status bit
This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY and CHRBUSY.
1 = At least one processing unit is busy
0 = None of the processing units is busy
bit 14-8 Unimplemented: Read as ‘0’
bit 7 IPUBUSY: Inflate Processing Unit Busy Status bit
1 = IPU is busy
0 = IPU is not busy
bit 6 RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit
1 = RCCGPU is busy
0 = RCCGPU is not busy
bit 5 CHRBUSY: Character Graphics Processing Unit Busy Status bit
1 = CHRGPU is busy
0 = CHRGPU is not busy
bit 4 VMRGN: Vertical Blanking Status bit
1 = Display interface is in the vertical blanking period
0 = Display interface is not in the vertical blanking period
bit 3 HMRGN: Horizontal Blanking Status bit
1 = Display interface is in the horizontal blanking period
0 = Display interface is not in the horizontal blanking period
bit 2 CMDLV: Command Watermark Level Status bit
The number of commands in the command FIFO changed from equal (=) to the command watermark value,
to less than (<) the command watermark value set in the GCMDWMK (G1CON1<12:8>) register bits.
1 = Command in FIFO is less than the set GCMDWMK value
0 = Command in FIFO is equal to, or greater than, the set GCMDWMK value
bit 1 CMDFUL: Command FIFO Full Status bit
1 = Command FIFO is full
0 = Command FIFO is not full
bit 0 CMDMPT: Command FIFO Empty Status bit
1 = Command FIFO is empty
0 = Command FIFO is not empty
© 2009 Microchip Technology Inc. DS39731A-page 43-11
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-7: G1IE: Interrupt Enable Register
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PUIE — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPUIE RCCIE CHRIE VMRGNIE HMRGNIE CMDLVIE CMDFULIE CMDMPTIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PUIE: Processing Units Complete Interrupt Enable bit
1 = Enables the PU complete interrupt
0 = Disables the PU complete interrupt
bit 14-8 Unimplemented: Read as ‘0’
bit 7 IPUIE: Inflate Processing Unit Complete Interrupt Enable bit
1 = Enables the IPU complete interrupt
0 = Disables the IPU complete interrupt
bit 6 RCCIE: Rectangle Copy Graphics Processing Unit Complete Interrupt Enable bit
1 = Enables the RCCGPU complete interrupt
0 = Disables the RCCGPU complete interrupt
bit 5 CHRIE: Character Graphics Processing Unit Complete Interrupt Enable bit
1 = Enables the CHRGPU complete interrupt
0 = Disables the CHRGPU complete interrupt
bit 4 VMRGNIE: Vertical Blanking Interrupt Enable bit
1 = Enables the vertical blanking period interrupt
0 = Disables the vertical blanking period interrupt
bit 3 HMRGNIE: Horizontal Blanking Interrupt Enable bit
1 = Enables the horizontal blanking period interrupt
0 = Disables the horizontal blanking period interrupt
bit 2 CMDLVIE: Command Watermark Interrupt Enable bit
1 = Enables the command watermark interrupt bit
0 = Disables the command watermark interrupt bit
bit 1 CMDFULIE: Command FIFO Full Interrupt Enable bit
1 = Enables the command FIFO full interrupt
0 = Disables the command FIFO full interrupt
bit 0 CMDMPTIE: Command FIFO Empty Interrupt Enable bit
1 = Enables the command FIFO empty interrupt
0 = Disables the command FIFO empty interrupt
PIC24F Family Reference Manual
DS39731A-page 43-12 © 2009 Microchip Technology Inc.
Register 43-8: G1IR: Interrupt Status Register
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PUIF — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPUIF RCCIF CHRIF VMRGNIF HMRGNIF CMDLVIF CMDFULIF CMDMPTIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PUIF: Processing Units Complete Interrupt Flag bit
PUIF is an ORed combination of IPUIF, RCCIF and CHRIF.
1 = One or more PUs completed command execution (must be cleared in software)
0 = All PUs are Idle or busy completing command execution
bit 14-8 Unimplemented: Read as ‘0’
bit 7 IPUIF: Inflate Processing Unit Complete Interrupt Flag bit
1 = IPU completed command execution (must be cleared in software)
0 = IPU is Idle or busy completing command execution
bit 6 RCCIF: Rectangle Copy Graphics Processing Unit Complete Interrupt Flag bit
1 = RCCGPU completed command execution (must be cleared in software)
0 = RCCGPU is Idle or busy completing command execution
bit 5 CHRIF: Character Graphics Processing Unit Complete Interrupt Flag bit
1 = CHRGPU completed command execution (must be cleared in software)
0 = CHRGPU is Idle or busy completing command execution
bit 4 VMRGNIF: Vertical Blanking Interrupt Flag bit
1 = Display interface is in the vertical blanking period (must be cleared in software)
0 = Display interface is not in the vertical blanking period
bit 3 HMRGNIF: Horizontal Blanking Interrupt Flag bit
1 = Display interface is in the horizontal blanking period (must be cleared in software)
0 = Display interface is not in the horizontal blanking period
bit 2 CMDLVIF: Command Watermark Interrupt Flag bit
1 = Command watermark level is reached (must be cleared in software)
0 = Command watermark level is not yet reached
bit 1 CMDFULIF: Command FIFO Full Interrupt Flag bit
1 = Command FIFO is full (must be cleared in software)
0 = Command FIFO is not full
bit 0 CMDMPTIF: Command FIFO Empty Interrupt Flag bit
1 = Command FIFO is empty (must be cleared in software)
0 = Command FIFO is not empty
© 2009 Microchip Technology Inc. DS39731A-page 43-13
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-9: G1W1ADRL: GPU Work Area 1 Start Address Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR15 W1ADR14 W1ADR13 W1ADR12 W1ADR11 W1ADR10 W1ADR9 W1ADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR7 W1ADR6 W1ADR5 W1ADR4 W1ADR3 W1ADR2 W1ADR1 W1ADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 W1ADR<15:0>: GPU Work Area 1 Start Address Low bits
Work area address must point to an even byte address in memory.
Register 43-10: G1W1ADRH: GPU Work Area 1 Start Address Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR23 W1ADR22 W1ADR21 W1ADR20 W1ADR19 W1ADR18 W1ADR17 W1ADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 W1ADR<23:16>: GPU Work Area 1 Start Address High bits
Work area address must point to an even byte address in memory.
PIC24F Family Reference Manual
DS39731A-page 43-14 © 2009 Microchip Technology Inc.
Register 43-11: G1W2ADRL: GPU Work Area 2 Start Address Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR15 W2ADR14 W2ADR13 W2ADR12 W2ADR11 W2ADR10 W2ADR9 W2ADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR7 W2ADR6 W2ADR5 W2ADR4 W2ADR3 W2ADR2 W2ADR1 W2ADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 W2ADR<15:0>: GPU Work Area 2 Start Address Low bits
Work area address must point to an even byte address in memory.
Register 43-12: G1W2ADRH: GPU Work Area 2 Start Address Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR23 W2ADR22 W2ADR21 W2ADR20 W2ADR19 W2ADR18 W2ADR17 W2ADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 W2ADR<23:16>: GPU Work Area 2 Start Address High bits
Work area address must point to an even byte address in memory.
© 2009 Microchip Technology Inc. DS39731A-page 43-15
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-13: G1PUW: GPU Work Area Width Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PUW10 PUW9 PUW8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PUW7 PUW6 PUW5 PUW4 PUW3 PUW2 PUW1 PUW0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 PUW<10:0>: GPU Work Area Width bits (in pixels)
Register 43-14: G1PUH: GPU Work Area Height Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PUH10 PUH9 PUH8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PUH7 PUH6 PUH5 PUH4 PUH3 PUH2 PUH1 PUH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 PUH<10:0>: GPU Work Area Height bits (in pixels)
PIC24F Family Reference Manual
DS39731A-page 43-16 © 2009 Microchip Technology Inc.
Register 43-15: G1DPADRL: Display Buffer Start Address Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR15 DPADR14 DPADR13 DPADR12 DPADR11 DPADR10 DPADR9 DPADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR7 DPADR6 DPADR5 DPADR4 DPADR3 DPADR2 DPADR1 DPADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DPADR<15:0>: Display Buffer Start Address Low bits
Display buffer start address must point to an even byte address in memory.
Register 43-16: G1DPADRH: Display Buffer Start Address Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR23 DPADR22 DPADR21 DPADR20 DPADR19 DPADR18 DPADR17 DPADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 DPADR<23:16>: Display Buffer Start Address High bits
Display buffer start address must point to an even byte address in memory.
© 2009 Microchip Technology Inc. DS39731A-page 43-17
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-17: G1DPW: Display Buffer Width Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DPW10 DPW9 DPW8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPW7 DPW6 DPW5 DPW4 DPW3 DPW2 DPW1 DPW0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 DPW<10:0>: Display Frame Width bits (in pixels)
Register 43-18: G1DPH: Display BUFFER Height Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DPH10 DPH9 DPH8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 DPH<10:0>: Display Frame Height bits (in pixels)
PIC24F Family Reference Manual
DS39731A-page 43-18 © 2009 Microchip Technology Inc.
Register 43-19: G1DPWT: Display Total Width Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DPWT10 DPWT9 DPWT8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPWT7 DPWT6 DPWT5 DPWT4 DPWT3 DPWT2 DPWT1 DPWT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 DPWT<10:0>: Display Total Width bits (in pixels)
Register 43-20: G1DPHT: Display Total Height Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DPHT10 DPHT9 DPHT8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPHT7 DPHT6 DPHT5 DPHT4 DPHT3 DPHT2 DPHT1 DPHT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 DPHT<10:0>: Display Total Height bits (in pixels)
© 2009 Microchip Technology Inc. DS39731A-page 43-19
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-21: G1ACTDA: Active Display Area Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ACTLINE7 ACTLINE6 ACTLINE5 ACTLINE4 ACTLINE3 ACTLINE2 ACTLINE1 ACTLINE0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ACTPIX7 ACTPIX6 ACTPIX5 ACTPIX4 ACTPIX3 ACTPIX2 ACTPIX1 ACTPIX0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 ACTLINE<7:0>: Number of Lines Before the First Active (displayed) Line bits
Typically, ACTLINE = VENST (G1DBLCON<15:8>). This register is added for versatility in the timing
of the active lines. For TFT mode, the DPMODE bits (G1CON2<2:0>) = 001 and the minimum value
is 2. For STN mode, the DPMODE bits (G1CON2<2:0>) = 010, 011, 100 0 and the minimum value is ‘ ’.
bit 7-0 ACTPIX<7:0>: Number of Pixels Before the First Active (displayed) Pixel bits (in DISPCLKs)
Typically, ACTPIX = HENST (G1DBLCON<7:0>). This register is added for versatility in the timing of
the active pixels. Note that the programmed value is computed in DISPCLK cycles. This value is
dependent on DPGWDTH (G1CON2<15:14>). Refer to Figure 43-12 for details.
Register 43-22: G1HSYNC: Horizontal Synchronization Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HSLEN7 HSLEN6 HSLEN5 HSLEN4 HSLEN3 HSLEN2 HSLEN1 HSLEN0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HSST7 HSST6 HSST5 HSST4 HSST3 HSST2 HSST1 HSST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs)
DPHSOE (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is ‘1’.
bit 7-0 HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs)
This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active.
PIC24F Family Reference Manual
DS39731A-page 43-20 © 2009 Microchip Technology Inc.
Register 43-23: G1VSYNC: Vertical Synchronization Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VSLEN7 VSLEN6 VSLEN5 VSLEN4 VSLEN3 VSLEN2 VSLEN1 VSLEN0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VSST7 VSST6 VSST5 VSST4 VSST3 VSST2 VSST1 VSST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 VSLEN<7:0>: VSYNC Pulse-Width Configuration bits (in lines)
DPVSOE (G1CON3<1>) must be set for VSYNC signal to toggle; minimum value is ‘1’.
bit 7-0 VSST<7:0>: VSYNC Start Delay Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the start of VSYNC active.
Register 43-24: G1DBLCON: Display Blanking Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VENST7 VENST6 VENST5 VENST4 VENST3 VENST2 VENST1 VENST0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HENST7 HENST6 HENST5 HENST4 HENST3 HENST2 HENST1 HENST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 VENST<7:0>: Vertical Blanking Start to First Displayed Line Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the first displayed line of a frame.
bit 7-0 HENST<7:0>: Horizontal Blanking Start to First Displayed Pixel Configuration bits (in DISPCLKs)
This is the number of DISPCLK cycles from the start of horizontal blanking to the first displayed pixel of
each displayed line.
© 2009 Microchip Technology Inc. DS39731A-page 43-21
Section 43. Graphics Controller Module (GFX)
Graphics Controller
Module (GFX)
43
Register 43-25: G1CLUT: Color Look-up Table Control Register
R/W-0 R-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CLUTEN CLUTBUSY — — — — CLUTTRD CLUTRWEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLUTADR7 CLUTADR6 CLUTADR5 CLUTADR4 CLUTADR3 CLUTADR2 CLUTADR1 CLUTADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CLUTEN: Color Look-up Table Enable Control bit
1 = Color look-up table enabled
0 = Color look-up table disabled
bit 14 CLUTBUSY: Color Look-up Table Busy Status bit
1 = A CLUT entry read/write access is being executed
0 = No CLUT entry read/write access is being executed
bit 13-10 Unimplemented: Read as ‘0’
bit 9 CLUTTRD: Color Look-up Table Read Trigger bit
Enabling this bit will trigger a read to the CLUT location determined by the CLUTADR bits
(G1CLUT<7:0>) with CLUTRWEN enabled.
1 = CLUT read trigger enabled (must be cleared in software after reading data in G1CLUTRD register)
0 = CLUT read trigger disabled
bit 8 CLUTRWEN: Color Look-up Table Read/Write Enable Control bit
This bit must be set when reading or modifying entries on the CLUT and it must also be cleared when
CLUT is used by the display controller. Refer to Section 43.3.4.1 “Reading and Writing CLUT
Entries” for details.
1 = Color look-up table read/write enabled; display controller cannot access the CLUT
0 = Color look-up table read/write disabled; display controller can access the CLUT
bit 7-0 CLUTADR<7:0>: Color Look-up Table Memory Address bits
PIC24F Family Reference Manual
DS39731A-page 43-22 © 2009 Microchip Technology Inc.
Register 43-26: G1CLUTWR: CLUT Memory Write Data Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLUTWR15 CLUTWR14 CLUTWR13 CLUTWR12 CLUTWR11 CLUTWR10 CLUTWR9 CLUTWR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLUTWR7 CLUTWR6 CLUTWR5 CLUTWR4 CLUTWR3 CLUTWR2 CLUTWR1 CLUTWR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CLUTWR<15:0>: Color Look-up Table Memory Write Data bits
A word write or a high byte write to this register triggers a write to the CLUT memory at the address
pointed to by the CLUTADR bits. Low byte write to this register will only update the G1CLUTWR<7:0>
bits and no write to CLUT memory will be triggered. During power-up and power-down of the display,
the most recent data written to this register will be used to control the timing of the GPWR signal. Refer
to Section 43.7 “Display Power Sequencing” for details.
Register 43-27: G1CLUTRD: CLUT Memory Read Data Register
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CLUTRD15 CLUTRD14 CLUTRD13 CLUTRD12 CLUTRD11 CLUTRD10 CLUTRD9 CLUTRD8
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CLUTRD7 CLUTRD6 CLUTRD5 CLUTRD4 CLUTRD3 CLUTRD2 CLUTRD1 CLUTRD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CLUTRD<15:0>: Color Look-up Table Memory Read Data bits
This register contains the most recent read from the CLUT memory pointed to by the CLUTADR
(G1CLUT<7:0>) bits. Reading of the CLUT memory is triggered when the CLUTTRD (G1CLUT<9>) bit
goes from ‘0’ to ‘1’.

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