Microchip PIC24HJ256GP206A Manual

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© 2006-2012 Microchip Technology Inc. DS70183D-page 16-1
Analog-to-Digital
Converter (ADC)
16
Section 16. Analog-to-Digital Converter (ADC)
HIGHLIGHTS
This section of the manual contains the following major topics:
16.1 Introduction .................................................................................................................. 16-2
16.2 Control Registers ......................................................................................................... 16-6
16.3 Overview of Sample and Conversion Sequence ....................................................... 16-17
16.4 ADC Configuration..................................................................................................... 16-27
16.5 ADC Interrupt Generation .......................................................................................... 16-33
16.6 Analog Input Selection for Conversion....................................................................... 16-35
16.7 Specifying Conversion Results Buffering for Devices with DMA................................ 16-44
16.8 ADC Configuration Example ...................................................................................... 16-48
16.9 ADC Configuration for 1.1 Msps ................................................................................16-49
16.10 Sample and Conversion Sequence Examples for Devices without DMA .................. 16-51
16.11 Sample and Conversion Sequence Examples for Devices with DMA ....................... 16-63
16.12 Analog-to-Digital Sampling Requirements ................................................................. 16-73
16.13 Reading the ADC Result Buffer .................................................................................16-74
16.14 Transfer Functions ..................................................................................................... 16-76
16.15 ADC Accuracy/Error................................................................................................... 16-78
16.16 Connection Considerations........................................................................................ 16-78
16.17 Operation During Sleep and Idle Modes .................................................................... 16-79
16.18 Effects of a Reset....................................................................................................... 16-79
16.19 Special Function Registers ........................................................................................ 16-80
16.20 Design Tips ................................................................................................................ 16-81
16.21 Related Application Notes.......................................................................................... 16-82
16.22 Revision History ......................................................................................................... 16-83
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-2 © 2006-2012 Microchip Technology Inc.
16.1 INTRODUCTION
This document describes the features and associated operational modes of the Successive
Approximation (SAR) Analog-to-Digital Converter (ADC) available on the dsPIC33F/PIC24H
families of devices.
The ADC module can be configured by the user application to function as a 10-bit, 4-channel
ADC (for devices with 10-bit only ADC) or a 12-bit, single-channel ADC (for devices with
selectable 10-bit or 12-bit ADC).
Figure 16-1 illustrates a block diagram of the ADC module for devices with DMA. Figure 16-2
illustrates a block diagram of the ADC module for devices without DMA.
The dsPIC33F/PIC24H ADC module has the following key features:
• SAR conversion
• Up to 1.1 Msps conversion speed
• Up to 32 analog input pins
• External voltage reference input pins
• Four unipolar differential Sample and Hold (S&H) amplifiers
• Simultaneous sampling of up to four analog input pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Up to 16-word conversion result buffer
• Selectable Buffer Fill modes (not available on all devices)
• DMA support, including Peripheral Indirect Addressing (not available on all devices)
• Operation during CPU Sleep and Idle modes
Depending on the device variant, the ADC module may have up to 32 analog input pins,
designated AN0-AN31. These analog inputs are connected by multiplexers to four S&H
amplifiers, designated CH0-CH3. The analog input multiplexers have two sets of control bits,
designated as MUXA (CHySA/CHyNA) and MUXB (CHySB/CHyNB). These control bits select a
particular analog input for conversion. The MUXA and MUXB control bits can alternatively select
the analog input for conversion. Unipolar differential conversions are possible on all channels
using certain input pins (see Figure 16-1 Figure 16-2 and ).
Channel Scan mode can be enabled for the CH0 S&H amplifier. Any subset of the analog inputs
(AN0 to AN31 based on availability) can be selected by the user application. The selected inputs
are converted in ascending order using CH0.
The ADC module supports simultaneous sampling using multiple S&H channels to sample the
inputs at the same time, and then performs the conversion for each channel sequentially. By
default, the multiple channels are sampled and converted sequentially.
For devices with DMA, the ADC module is connected to a single-word result buffer. However,
multiple conversion results can be stored in a DMA RAM buffer with no CPU overhead when
DMA is used with the ADC module. Each conversion result is converted to one of four 16-bit
output formats when it is read from the buffer.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33F/PIC24H devices.
Please consult the note at the beginning of the “Analog-to-Digital Converter
(ADC)” chapter in the current device data sheet to check whether this document
supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-5
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Figure 16-2: ADC Block Diagram for Devices without DMA
SAR ADC
S/H0
S/H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN31
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
AN9
VREFL
CH123SB
CH123NA CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
AN10
VREFL
CH123SB
CH123NA CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
AN11
VREFL
CH123SB
CH123NA CH123NB
AN8
+
-
CH1(2)
CH0
CH2(2)
CH3(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For details, refer to the “Pin Diagrams” section in the specific device
data sheet.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
Input Selection
VREFH VREFL
V +REF (1) AV AVDD SS
V -REF (1)
VCFG<2:0>
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-6 © 2006-2012 Microchip Technology Inc.
16.2 CONTROL REGISTERS
The ADC module has ten Control and Status registers. These registers are:
•ADxCON1: ADCx Control Register 1
•ADxCON2: ADCx Control Register 2
•ADxCON3: ADCx Control Register 3
•ADxCON4: ADCx Control Register 4
•ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register
•ADxCHS0: ADCx Input Channel 0 Select Register
•AD1CSSH: ADC1 Input Scan Select Register High
•ADxCSSL: ADCx Input Scan Select Register Low
•AD1PCFGH: ADC1 Port Configuration Register High
•ADxPCFGL: ADCx Port Configuration Register Low
The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.
The ADxCON4 register sets up the number of conversion results stored in a DMA buffer for each
analog input in the Scatter/Gather mode for devices with DMA. The ADxCHS123 and ADxCHS0
registers select the input pins to be connected to the S&H amplifiers. The ADCSSH/L registers
select inputs to be sequentially scanned. The ADxPCFGH/L registers configure the analog input
pins as analog inputs or as digital I/O.
16.2.1 ADC Result Buffer
For devices with DMA, the ADC module contains a single-word result buffer, ADC1BUF0. For
devices without DMA, the ADC module contains a 16-word dual-port RAM, to buffer the results.
The 16 buffer locations are referred to as ADC1BUF0, ADC1BUF1, ADC1BUF2, ..., ADC1BUFE
and ADC1BUFF.
Note: After a device reset, the ADC buffer register(s) will contain unknown data.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-9
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-2: ADxCON2: ADCx Control Register 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG<2:0> — — CSCNA CHPS<1:0>
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0>(1,2) BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scan inputs for CH0+ during Sample A bit
0 = Do not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer. The user application should access data in the
first half of the buffer
0 = ADC is currently filling the first half of the buffer. The user application should access data in the
second half of the buffer
bit 6 Unimplemented: Read as ‘0’
Note 1: For devices with DMA, the SMPI<3:0> bits are referred to as the Increment Rate for DMA Address Select
bits.
2: For devices without DMA, the SMPI<3:0> bits are referred to as the Number of Samples Per Interrupt
Select bits.
3: The VREF+ and VREF- pins are not available on all devices. Refer to the “Pin Diagrams” section in the
specific device data sheet for availability.
VREFH VREFL
000 AVDD AVss
001 External VREF+(3) AVss
010 AVDD External VREF-(3)
011 External VREF+(3) External VREF-(3)
1xx AVDD AVss
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-10 © 2006-2012 Microchip Technology Inc.
bit 5-2 SMPI<3:0>: Sample and Conversion Operation bits(1,2)
For devices with DMA:
1111 = Increments the DMA address after completion of every 16th sample/conversion operation
1110 = Increments the DMA address after completion of every 15th sample/conversion operation
•
•
•
0001 = Increments the DMA address after completion of every 2nd sample/conversion operation
0000 = Increments the DMA address after completion of every sample/conversion operation
For devices without DMA:
1111 = ADC interrupt is generated at the completion of every 16th sample/conversion operation
1110 = ADC interrupt is generated at the completion of every 15th sample/conversion operation
•
•
•
0001 = ADC interrupt is generated at the completion of every 2nd sample/conversion operation
0000 = ADC interrupt is generated at the completion of every sample/conversion operation
bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts filling the first half of the buffer on the first interrupt and the second half of the buffer on the
next interrupt
0 = Always starts filling the buffer from the start address
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
Register 16-2: ADxCON2: ADCx Control Register 2 (Continued)
Note 1: For devices with DMA, the SMPI<3:0> bits are referred to as the Increment Rate for DMA Address Select
bits.
2: For devices without DMA, the SMPI<3:0> bits are referred to as the Number of Samples Per Interrupt
Select bits.
3: The VREF+ and VREF- pins are not available on all devices. Refer to the “Pin Diagrams” section in the
specific device data sheet for availability.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-11
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-3: ADxCON3: ADCx Control Register 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — — SAMC<4:0>(1,2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC Internal RC Clock
0 = Clock Derived from System Clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto Sample Time bits(1,2)
11111 = 31 TAD
•
•
•
00001 = 1 T
AD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = Reserved
•
•
•
01000000 = Reserved
00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD
•
•
•
00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD
00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD
00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD
Note 1: This bit is only used when the SSRC<2:0> bits (ADxCON1<7:5>) = 111.
2: If SSRC<2:0> = 111, the SAMC bit should be set to at least ‘1’ when using one S&H channel or using
simultaneous sampling. When using multiple S&H channels with sequential sampling, the SAMC bit
should be set to ‘0’ for the fastest possible conversion rate.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-14 © 2006-2012 Microchip Technology Inc.
Register 16-6: ADxCHS0: ADCx Input Channel 0 Select Register
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — CH0SB<4:0>(1)
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA — — CH0SA<4:0>(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
(1)
Same definition as bit<4:0>.
bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REFL
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1,2)
11111 = Channel 0 positive input is AN31
11110 = Channel 0 positive input is AN30
•
•
•
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
Note 1: The AN16 through AN31 pins are not available for ADC2.
2: These bits have no effect when the CSCNA bit (ADxCON2<10>) = 1.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-17
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.3 OVERVIEW OF SAMPLE AND CONVERSION SEQUENCE
Figure 16-3 illustrates that the analog-to-digital conversion is a three step process:
1. The input voltage signal is connected to the sample capacitor.
2. The sample capacitor is disconnected from the input.
3. The stored voltage is converted to equivalent digital bits.
The two distinct phases, sample and conversion, are independently controlled.
Figure 16-3: Sample Conversion Sequence
16.3.1 Sample Time
Sample Time is when the selected analog input is connected to the sample capacitor. There is a
minimum sample time to ensure that the S&H amplifier provides a desired accuracy for the
analog-to-digital conversion (see 16.12 “Analog-to-Digital Sampling Requirements”).
The sampling phase can be set up to start automatically upon conversion or by manually setting
the Sample bit (SAMP) in the ADC Control Register 1 (ADxCON1<1>). The sampling phase is
controlled by the Auto-Sample bit (ASAM) in the ADC Control Register 1 (ADxCON1<2>).
Table 16-1 lists the options selected by the specific bit configuration.
Table 16-1: Start of Sampling Selection
If automatic sampling is enabled, the sampling time (TSMP) taken by the ADC module is equal to
the number of TAD cycles defined by the SAMC<4:0> bits (ADxCON3<12:8>), as shown by
Equation 16-1.
Equation 16-1: Sampling Time Calculation
If manual sampling is desired, the user software must provide sufficient time to ensure adequate
sampling time.
+
-
+
-
SAR
ADC
Sample Time Conversion Time
SOC
Trigger
Note: The ADC module requires a finite number of analog-to-digital clock cycles to start
conversion after receiving a conversion trigger or stopping the sampling process.
Refer to the TPCS parameter in the “Electrical Characteristics” chapter of the spe-
cific device data sheet for further details.
ASAM Start of Sampling Selection
0Manual sampling
1Automatic sampling
TSMP = SAMC<4:0> • TAD

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