Microchip PIC32MZ1064DAB288 Manual

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Section 22. 12-bit High-Speed Successive Approximation

This section of the manual contains the following major topics:

22.1 Introduction .................................................................................................................. 22-2

22.2 Control Registers ......................................................................................................... 22-6

22.3 ADC Operation........................................................................................................... 22-61

22.4 ADC Module Configuration ........................................................................................ 22-65

22.5 Additional ADC Functions .......................................................................................... 22-85

22.6 Interrupts.................................................................................................................. 22-108

22.7 Operation During Power-Saving Modes .................................................................. 22-114

22.8 Effects of Reset........................................................................................................ 22-116

22.9 Transfer Function..................................................................................................... 22-116

22.10 ADC Sampling Requirements.................................................................................. 22-117

22.11 Connection Considerations...................................................................................... 22-117

22.12 Related Application Notes........................................................................................ 22-118

22.13 Revision History ....................................................................................................... 22-119

PIC32 Family Reference Manual

22.1 INTRODUCTION

The PIC32 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital

Converter (ADC) includes the following features:

• 12-bit resolution

• Up to eight ADC modules with dedicated Sample and Hold (S&H) circuits (see Note 1)

• Two dedicated ADC modules can be combined in Turbo mode to provide double

conversion rate

• Single-ended and/or differential inputs

• Can operate during Sleep mode

• Supports touch sense applications

• Up to six digital comparators

• Up to six digital filters supporting two modes:

- Oversampling mode

- Averaging mode

• FIFO and DMA engine for dedicated ADC modules (see Note 2)

• Early interrupt generation resulting in faster processing of converted data

• Designed for motor control, power conversion, and general purpose applications

The dedicated ADC modules use a single input (or its alternate) and is intended for high-speed

and precise sampling of time-sensitive or transient inputs, whereas the shared ADC module

incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling,

and provides flexible automated scanning option through the input scan logic.

For each ADC module, the analog inputs are connected to the S&H capacitor. The clock,

sampling time, and output data resolution for each ADC module can be set independently. The

ADC module performs the conversion of the input analog signal based on the configurations set

in the registers. When conversion is complete, the final result is stored in the result buffer for the

specific analog input and is passed to the digital filter and digital comparator if configured to use

data from this particular sample.

A simplified block diagram of the ADC module is illustrated in Figure 22-1.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device, this manual section may not apply to all

PIC32 devices.

Please refer to the note at the beginning of the “ADC” chapter in the current device

data sheet to check whether this document supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note 1: Depending on the device, the 12-bit High-Speed SAR ADC has up to seven

dedicated ADC modules and one shared ADC module. Throughout this chapter,

the diagrams and code examples refer to a device with seven dedicated ADC

modules (ADC0-ADC6) and one shared ADC (ADC7). Please consult the “ADC”

chapter in the specific device data sheet to determine which ADC modules are

available for your device.

2: This feature is not available on all devices. Refer to the “ADC” chapter in the

specific device data sheet to determine availability.

3: Prior to enabling the ADC module, the user application must copy the ADC

calibration data (DEVADCx) from the Configuration memory into the ADC

Configuration registers (ADC0CFG-ADC7CFG). Refer to the “ADC” chapter in the

specific device data sheet for more information.

Section 22. 12-bit High-Speed SAR ADC

Figure 22-1: ADC Block Diagram

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

ADC0

ADC7

REF

+ V

REF

VREFSEL<2:0>

REFH

REFL

ADCSEL<1:0>

CONCLKDIV<5:0>

FRC PBCLK

ADCDIV<6:0>

(ADCxTIME<22:16>)

ADCDIV<6:0>

(ADCCON2<6:0>)

AD0

-T

AD6

AD7

ADDATA0

…...

ADDATA63

(Dedicated

ADC)

(Dedicated

ADC)

FIFO

DMA

Digital Filter

Digital Comparator Interrupt/Event

Capacitive Voltage

Divider (CVD) Interrupt/Event

Triggers,

Turbo Channel,

Scan Control Logic

Trigger

Status and Control

Registers

ADC6

SH0ALT<1:0>

(ADCTRGMODE<17:16>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

ANa

AN1

REFL

DIFF1<1>

(ADCIMCON1<3>)

SH6ALT<1:0>

(ADCTRGMODE<29:28>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

AN49

CTMU

BAT

AN48

AN7

CVD

Capacitor

CLK

ANb

ANc

ANd

ANb

ANc

ANd

SYSTEMBUS

ANa

Interrupt

Data

PIC32 Family Reference Manual

Figure 22-2: FIFO Block Diagram

FEN

(ADCFSTAT<31>

FIFO

(Depth Device Dependent)

ADCFIFO DATA<31:0>

ADCID<2:0>

ADCFSTAT<2:0> ADCx ID

ADCx ID Converted Data

ADC6

ADC6EN

(ADCFSTAT<30>)

ADC5

ADC5EN

(ADCFSTAT<29>)

ADC0

ADC0EN

(ADCFSTAT<24>)

If data

available in

FIFO

FRDY

ADCFSTAT<22>

FIEN

(ADCFSTAT<23>

Interrupt

FCNT<7:0>

ADCFSTAT<15:8>

(Number of data in FIFO)

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

Section 22. 12-bit High-Speed SAR ADC

Figure 22-3: DMA Block Diagram

DMAGEN

(ADCDMASTAT<31>)

ADC6

DMAEN

(ADC6TIME<23>)

ADC5

ADC0

DMAEN

(ADC5TIME<23>)

DMAEN

(ADC0TIME<23>)

Buffer A (ADC0)

Buffer B (ADC0)

Buffer A (ADC1)

Buffer B (ADC1)

Buffer A (ADC6)

Buffer B (ADC6)

DMABL<2:0>

Buffer

Full?

RAF0

(ADCDMASTAT<0>)

RAFIEN0

(ADCDMASTAT<8>)

Interrupt

Buffer

Full?

RBF6

(ADCDMASTAT<22>)

RBFIEN6

(ADCDMASTAT<30>)

Interrupt

Data Count for Buffer-A

(ADC0)

Data Count for Buffer-B

(ADC0)

Data Count for Buffer-A

(ADC1)

Data Count for Buffer-B

(ADC1)

Data Count for Buffer-A

(ADC6)

Data Count for Buffer-B

(ADC6)

DMABADDR<31:0>

CNTBADDR<31:0>

CNTBADDR<31:0> + 1

CNTBADDR<31:0> + 2

CNTBADDR<31:0> + 3

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

ADCTRG6

31:16 — — — TRGSRC23<4:0> —— —

15:0 — — — TRGSRC21<4:0> —— —

ADCTRG7

31:16 — — — TRGSRC27<4:0> —— —

15:0 — — — TRGSRC25<4:0> —— —

ADCTRG8

31:16 — — — TRGSRC31<4:0> —— —

15:0 — — — TRGSRC29<4:0> —— —

ADCCMPCON1

31:16 CVDDATA<15:0>

15:0 — — AINID<5:0> ENDCMP DCMPGIEN DCMPED IEBTWN I

ADCCMPCONx

‘x’ = 2-6

31:16 — — — — — — — — — — — —

15:0 — — — AINID<4:0> ENDCMP DCMPGIEN DCMPED IEBTWN I

ADCFSTAT

31:16 FEN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN FIEN FRDY FWROVERR —

15:0 FCNT<7:0> FSIGN — — —

ADCFIFO

31:16 DATA<31:16>

15:0 DATA<15:0>

ADCBASE

31:16 — — — — — — — — — — — —

15:0 ADCBASE<15:0>

ADCDMASTAT

31:16 DMAGEN RBFIEN6 RBFIEN5 RBFIEN4 RBFIEN3 RBFIEN2 RBFIEN1 RBFIEN0 DMAWROVERR RBF6 RBF5 RBF4

15:0 DMACNTEN RAFIEN6 RAFIEN5 RAFIEN4 RAFIEN3 RAFIEN2 RAFIEN1 RAFIEN0 — RAF6 RAF5 RAF4

ADCCNTB

31:16 CNTBADDR<31:16>

15:0 CNTBADDR<15:0>

ADCDMAB

31:16 DMABADDR<31:16>

15:0 DMABADDR<15:0>

ADCTRGSNS

31:16 LVL31 LVL30 LVL29 LVL28 LVL27 LVL26 LVL25 LVL24 LVL23 LVL22 LVL21 LVL20

15:0 LVL15 LVL14 LVL13 LVL12 LVL11 LVL10 LVL9 LVL8 LVL7 LVL6 LVL5 LVL4

ADCxTIME

‘x’ = 0-6

31:16 — — — ADCEIS<2:0> SELRES<1:0> DMAEN ADC

15:0 — — — — — — SAMC<9:0>

ADCEIEN1

31:16 EIEN31 EIEN30 EIEN29 EIEN28 EIEN27 EIEN26 EIEN25 EIEN24 EIEN23 EIEN22 EIEN21 EIEN20 E

15:0 EIEN15 EIEN14 EIEN13 EIEN12 EIEN11 EIEN10 EIEN9 EIEN8 EIEN7 EIEN6 EIEN5 EIEN4

ADCEIEN2

31:16 EIEN63 EIEN62 EIEN61 EIEN60 EIEN59 EIEN58 EIEN57 EIEN56 EIEN55 EIEN54 EIEN53 EIEN52 E

15:0 EIEN47 EIEN46 EIEN45 EIEN44 EIEN43 EIEN42 EIEN41 EIEN40 EIEN39 EIEN38 EIEN37 EIEN36 E

ADCEISTAT1

31:16 EIRDY31 EIRDY30 EIRDY29 EIRDY28 EIRDY27 EIRDY26 EIRDY25 EIRDY24 EIRDY23 EIRDY22 EIRDY21 EIRDY20 E

15:0 EIRDY15 EIRDY14 EIRDY13 EIRDY12 EIRDY11 EIRDY10 EIRDY9 EIRDY8 EIRDY7 EIRDY6 EIRDY5 EIRDY4 E

ADCEISTAT2

31:16 EIRDY63 EIRDY62 EIRDY61 EIRDY60 EIRDY59 EIRDY58 EIRDY57 EIRDY56 EIRDY55 EIRDY54 EIRDY53 EIRDY52 E

15:0 EIRDY47 EIRDY46 EIRDY45 EIRDY44 EI DY39 EIRDY38 EIRDY37 EIRDY36 ERDY43 EIRDY42 EIRDY41 EIRDY40 EIR

ADCANCON

31:16 — — — — WKUPCLKCNT<3:0> WKIEN7 WKIEN6 WKIEN5 WKIEN4 W

15:0 WKRDY7 WKRDY6 WKRDY5 WKRDY4 WKRDY3 WKRDY2 WKRDY1 WKRDY0 ANEN7 ANEN6 ANEN5 ANEN4 A

ADCDATAx

('x' = 0 to 63)

31:16 DATA<31:16>

15:0 DATA<15:0>

ADCxCFG

‘x’ = 0-7

(1)

31:16 ADCCFG<31:16>

15:0 ADCCFG<15:0>

ADCSYSCFG0

31:16 AN<31:16>

15:0 AN<15:0>

ADCSYSCFG1

31:16 AN<63:48>

15:0 AN<47:32>

Table 22-1: ADC SFR Summary

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 B

Note 1: Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory-programmed DEVADCx Flash register

registers.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TRBEN TRBERR TRBMST<2:0> TRBSLV<2:0>

23:16

R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FRACT SELRES<1:0> STRGSRC<4:0>

15:8

R/W-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 U-0

ON — SIDL AICPMPEN CVDEN FSSCLKEN FSPBCLKEN —

7:0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— IRQVS<2:0> STRGLVL DMABL<2:0>

Legend: HC = Hardware Set HS = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 TRBEN: Turbo Channel Enable bit

1 = Enable the Turbo channel

0 = Disable the Turbo channel

bit 30 TRBERR: Turbo Channel Error Status bit

1 = An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless

of the TRBEN bit being set to ‘1’.

0 = Turbo channel error did not occur

Note: The status of this bit is valid only after the TRBEN bit is set.

bit 29-27 TRBMST<2:0>: Turbo Master ADCx bits

111 = Reserved

110 = ADC6 is selected as the Turbo Master

•

000 = ADC0 is selected as the Turbo Master

bit 26-24 TRBSLV<2:0>: Turbo Slave ADCx bits

111 = Reserved

110 = ADC6 is selected as the Turbo Slave

•

000 = ADC0 is selected as the Turbo Slave

bit 23 FRACT: Fractional Data Output Format bit

1 = Fractional

0 = Integer

bit 22-21 SELRES<1:0>: Shared ADC Resolution bits

11 = 12 bits (default)

10 = 10 bits

01 = 8 bits

00 = 6 bits

bit 20-16 STRGSRC<4:0>: Scan Trigger Source Select bits

11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections

00011 = Reserved

00010 = Global level software trigger (GLSWTRG) is not self-cleared

00001 = Global software trigger (GSWTRG) is self-cleared on the next clock cycle

00000 = No trigger

bit 15 ON: ADC Module Enable bit

1 = ADC module is enabled

0 = ADC module is disabled

Note: The ON bit should be set only after the ADC module has been configured.

bit 14 Unimplemented: Read as ‘0’

PIC32 Family Reference Manual

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0, HS, HC R-0, HS, HC R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BGVRRDY REFFLT EOSRDY CVDCPL<2:0> SAMC<9:9>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SAMC<7:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BGVRIEN REFFLTIEN EOSIEN ADCEIOVR ECRIEN ADCEIS<2:0>

7:0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADCDIV<6:0>

Legend: HC = Hardware Set HS = Hardware Cleared r = Reserved

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 BGVRRDY: Band Gap Voltage/ADC Reference Voltage Status bit

1 = Both band gap voltage and ADC reference voltages (V

REF

) are ready

0 = Either or both band gap voltage and ADC reference voltages (V

REF

) are not ready

Data processing is valid only after the BGVRRDY bit is set by hardware, hence the application code must

check that the BGVRRDY bit is set to ensure data validity. This bit is set to ‘ ’ when the ON bit0

(ADCCON1<15>) = 0.

bit 30 REFFLT: Band Gap/V

REF

/AV

BOR Fault Status bit

1 = Fault in band gap or the V

REF

voltage while the ON bit (ADCCON1<15>) was set. Most likely a band

gap or V

REF

fault will be caused by a BOR of the analog V

supply.

0 = Band gap and V

REF

voltage are working properly

This bit is cleared when the ON bit (ADCCON1<15>) = 0 and the BGVRRDY bit = 1.

bit 29 EOSRDY: End of Scan Interrupt Status bit

1 = All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in

the ADCCSS1 and ADCCSS2 registers) have completed scanning

0 = Scanning has not completed

This bit is cleared when ADCCON2<31:24> are read in software.

bit 28-26 CVDCPL<2:0>: Capacitor Voltage Divider (CVD) Setting bit

111 = 7 * 2.5 pF = 17.5 pF

110 = 6 * 2.5 pF = 15 pF

101 = 5 * 2.5 pF = 12.5 pF

100 = 4 * 2.5 pF = 10 pF

011 = 3 * 2.5 pF = 7.5 pF

010 = 2 * 2.5 pF = 5 pF

001 = 1 * 2.5 pF = 2.5 pF

000 = 0 * 2.5 pF = 0 pF

bit 25-16 SAMC<9:0>: Sample Time for the Shared ADC bits

1111111111 = 1025 T

•

0000000001 = 3 T

0000000000 = 2 T

Where T

= period of the ADC conversion clock for the Shared ADC controlled by the ADCDIV<6:0> bits.

bit 15 BGVRIEN: Band Gap/V

REF

Voltage Ready Interrupt Enable bit

1 = Interrupt will be generated when the BGVRRDY bit is set

0 = No interrupt is generated when the BGVRRDY bit is set

Section 22. 12-bit High-Speed SAR ADC

bit 14 REFFLTIEN: Band Gap/V

REF

Voltage Fault Interrupt Enable bit

1 = Interrupt will be generated when the REFFLT bit is set

0 = No interrupt is generated when the REFFLT bit is set

bit 13 EOSIEN: End of Scan Interrupt Enable bit

1 = Interrupt will be generated when EOSRDY bit is set

0 = No interrupt is generated when the EOSRDY bit is set

bit 12 ADCEIOVR: Early Interrupt Request Override bit

1 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1

and ADCGIRQEN2 registers

0 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1

and ADCEIEN2 registers

bit 11 ECRIEN: External Conversion Request Interface Enable bit

1 = Enables ADC conversion start from external module (such as PTG)

0 = External modules cannot start ADC conversion

bit 10-8 ADCEIS<2:0>: Shared ADC Early Interrupt Select bits

These bits select the number of clocks (T

)

prior to the arrival of valid data that the associated interrupt

is generated.

111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion

110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion

•

001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion

000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion

Note: All options are available when the selected resolution, set by the SELRES<1:0> bits

(ADCCON1<22:21>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’ to

‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ADCDIV<6:0>: Shared ADC Clock Divider bits

1111111 = 254 * T

= T

•

0000011 = 6 * T

= T

0000010 = 4 * T

= T

0000001 = 2 * T

= T

0000000 = Reserved

The ADCDIV<6:0> bits divide the ADC control clock (T

) to generate the clock for the Shared ADC (T

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCSEL<1:0> CONCLKDIV<5:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIGEN7

(5)

DIGEN6

(5)

DIGEN5

(5)

DIGEN4

(5)

DIGEN3

(5)

DIGEN2

(5)

DIGEN1

(5)

DIGEN0

(5)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R/W-0 R-0, HS, HC

VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP

(1,2,3,4)

RQCNVRT

7:0

R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GLSWTRG GSWTRG ADINSEL<5:0>

(5)

Legend: HC = Hardware Set HS = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 ADCSEL<1:0>: Analog-to-Digital Clock Source (T

CLK

) bits

Refer to the “12-bit High-Speed Successive Approximation Register (SAR)” chapter in the specific

device data sheet for the ADC Clock source selections.

bit 29-24 CONCLKDIV<5:0>: Analog-to-Digital Control Clock (T

) Divider bits

111111 = 126 * T

CLK

= T

•

000011 = 6 * T

CLK

= T

000010 = 4 * T

CLK

= T

000001 = 2 * T

CLK

= T

000000 = T

CLK

= T

bit 23 DIGEN7: ADC7 Digital Enable bit

(5)

1 = ADC7 is digital enabled

0 = ADC7 is digital disabled

bit 22 DIGEN6: ADC6 Digital Enable bit

(5)

1 = ADC6 is digital enabled

0 = ADC6 is digital disabled

bit 21 DIGEN5: ADC5 Digital Enable bit

(5)

1 = ADC5 is digital enabled

0 = ADC5 is digital disabled

bit 20 DIGEN4: ADC4 Digital Enable bit

(5)

1 = ADC4 is digital enabled

0 = ADC4 is digital disabled

Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the

bit is cleared. Also, usage of the SAMP bit will cause settings of the SAMC<9:0> bits (ADCCON2<25:16>)

to be ignored.

2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog

inputs are not affected by the SAMP bit.

3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit

and only after setting the RQCNVRT bit to start the analog-to-digital conversion.

4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and

STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them

from interfering with the software-controlled sampling command signal SAMP and with the

software-controlled trigger RQCNVRT.

5: Depending on the device, the function will vary. Refer to the “ADC” chapter in the specific device data

sheet to determine the function that is available for your device.

Section 22. 12-bit High-Speed SAR ADC

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — SH6ALT<1:0> SH5ALT<1:0> SH4ALT<1:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SH3ALT<1:0> SH2ALT<1:0> SH1ALT<1:0> SH0ALT<1:0>

15:8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— STRGEN6 STRGEN5 STRGEN4 STRGEN3 STRGEN2 STRGEN1 STRGEN0

7:0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— SSAMPEN6 SSAMPEN5 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘ ’

bit 29-28 SH6ALT<1:0>: ADC6 Analog Input Select bit