Microchip WFI32E03PC Manual

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Section 50. CPU for Devices with MIPS32® microAptiv™

and M-Class Cores

This section of the manual contains the following topics:

50.1 Introduction .................................................................................................................. 50-2

50.2 Architecture Overview.................................................................................................. 50-4

50.3 PIC32 CPU Details ...................................................................................................... 50-8

50.4 Special Considerations When Writing to CP0 Registers ........................................... 50-13

50.5 MIPS32 Architecture .................................................................................................. 50-14

50.6 CPU Bus .................................................................................................................... 50-15

50.7 Internal System Busses ............................................................................................. 50-15

50.8 Set/Clear/Invert .......................................................................................................... 50-16

50.9 ALU Status Bits.......................................................................................................... 50-16

50.10 Interrupt and Exception Mechanism .......................................................................... 50-17

50.11 Programming Model................................................................................................... 50-17

50.12 Floating Point Unit (FPU) ........................................................................................... 50-24

50.13 Coprocessor 0 (CP0) Registers ................................................................................. 50-42

50.14 Coprocessor 1 (CP1) Registers ............................................................................... 50-121

50.15 microMIPS Execution............................................................................................... 50-132

50.16 MCU ASE Extension ................................................................................................ 50-132

50.17 MIPS DSP ASE Extension ....................................................................................... 50-133

50.18 Memory Model (MCU only) ...................................................................................... 50-133

50.19 Memory Management (MPU only) ........................................................................... 50-135

50.20 L1 Caches (MPU only)............................................................................................. 50-141

50.21 CPU Instructions...................................................................................................... 50-145

50.22 MIPS DSP ASE Instructions .................................................................................... 50-151

50.23 CPU Initialization......................................................................................................50-153

50.24 Effects of a Reset.....................................................................................................50-154

50.25 Related Application Notes ........................................................................................ 50-155

50.26 Revision History ....................................................................................................... 50-156

PIC32 Family Reference Manual

50.1 INTRODUCTION

Depending on the device family, PIC32 devices are a complex System-on-Chip (SoC), which are

based on the microAptiv™ Microprocessor core or the M-Class Microprocessor core from

Imagination Technologies Ltd. This document provides an overview of the CPU system

architecture and features of PIC32 microcontrollers that feature these microprocessor cores.

The microAptiv Microprocessor core is a superset of the MIPS

® M14KE™ and M14KEc™

Microprocessor cores. These cores are state of the art, 32-bit, low-power, RISC processor cores

with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).

The M-Class Microprocessor core is a superset of the microAptiv™ Microprocessor core. This

32-bit, low-power, RISC processor core uses the enhanced MIPS32

® Release 5 Instruction Set

Architecture (ISA).

Visit the Imagination Technologies Ltd. website (www.imgtec.com) to learn more about the

microprocessor cores.

Depending on the core configuration, one of two options, MCU or MPU, are used, as shown in

Table 50-1.

Table 50-1: microAptiv and M-Class Microprocessor Core Configurations

The primary difference between the MCU and MPU is the presence of an L1 cache and

TLB-based MMU on the MPU. These features are used to facilitate PIC32 designs that use

operating systems to manage virtual memory.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “CPU” chapter in the current device

data sheet to check whether this document supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

MCU Features MPU Features

Split-bus architecture Unified bus architecture

Integrated DSP ASE (see Note 1) Integrated DSP ASE (see Note 1)

Integrated MCU™ ASE Integrated MCU ASE

microMIPS™ code compression microMIPS code compression

FMT-based MMU TLB-based MMU (see Note 1)

Two shadow register sets Eight shadow register sets

EJTAG TAP controller EJTAG TAP controller

Performance counters Performance counters

Hardware Trace (iFlowtrace®) Hardware Trace (iFlowtrace)

Level One (L1) CPU cache

Note 1: This feature is not available on all devices, refer to the “CPU” chapter of the spe-

cific device data sheet to determine availability.

Section 50. CPU for Devices with MIPS32® microAp-

50.1.1 Key Features Common to All PIC32 Devices with the microAptiv

Microprocessor Core

The following key features are common to all PIC32 devices that are based on the microAptiv

Microprocessor core:

• microMIPS variable-length instruction mode for compact code

• Vectored interrupt controller with up to 256 interrupt sources

• Atomic bit manipulations on peripheral registers (Single cycle)

• High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and

application data streaming functions

• EJTAG debug port allows extensive third party debug, programming and test tools support

• Instruction controlled power management modes

• Five-stage pipelined instruction execution

• Internal code protection to help protect intellectual property

• Arithmetic saturation and overflow handling support

• Zero cycle overhead saturation and rounding operations

• Atomic read-modify-write memory-to-memory instructions

• MAC instructions with up to 4 accumulators

• Native fractional data type (Q15, Q31) with rounding support

• Digital Signal Processing (DSP) Application-Specific Extension (ASE) Revision 2, which adds

DSP capabilities with support for powerful data processing operations

• Multiply/Divide unit with a maximum issue rate of one 32 x 32 multiply per clock

50.1.2 Key Features Common to All PIC32 Devices with the M-Class

Microprocessor Core

In addition to the features described for devices with the microAptiv core, the following key

features are common to all PIC32 devices that are based on the M-Class Microprocessor core:

• Implements the latest MIPS Release 5 Architecture, which includes IP protection and

reliability for industrial controllers, Internet of Things (IoT), wearables, wireless

communications, automotive, and storage

• Floating Point Unit (FPU)

50.1.3 Related MIPS Documentation

Related MIPS documentation is available for download from the related Imagination

Technologies Ltd. product page. Please note that a login may be required to access these

documents.

Documentation for the microAptiv core is available for download at:

http://www.imgtec.com/mips/aptiv/microaptiv.asp

Documentation for the M-Class core is available for download at:

http://www.imgtec.com/mips/warrior/mclass.asp

PIC32 Family Reference Manual

50.2 ARCHITECTURE OVERVIEW

The PIC32 family of devices are complex systems-on-a-chip that contain many features.

Included in all processors of the PIC32 family is a high-performance RISC CPU, which can be

programmed in 32-bit and 16-bit modes, and even mixed modes.

Devices with the M-Class core include a Floating Point Unit (FPU) that implements the MIPS

Release 5 Instruction Set Architecture for floating point computation. The FPU implementation

supports the ANSI/IEEE Standard 754 (IEEE Standard for Binary Floating-Point Arithmetic) for

single- and double-precision data formats.

PIC32 devices contain a high-performance Interrupt Controller, DMA controller, USB controller,

in-circuit debugger, a high-performance switching matrix for high-speed data accesses to the

peripherals, and on-chip data RAM memory, which holds data and programs. The optional

prefetch cache and prefetch buffer for the Flash memory, which hides the latency of the Flash,

provides zero Wait state equivalent performance.

Figure 50-1: PIC32 Block Diagram

Note: Refer to the “CPU” chapter in the specific device data sheet to determine availabil-

ity of the FPU module in your device.

JTAG/BSCAN Priority Interrupt

Controller LDO VREG

DMAC ICD

PIC32 CPU

System Bus

Prefetch Cache Data RAM

Peripheral

Flash Memory

Flash Controller

Clock Control/

Generation Reset Generation

PMP/PSP

PORTS

ADC

RTCC

Timers

Input Capture

PWM/Output

Compare

Comparators

SSP/SPI

I2C™

UART

128-bit

USB

Bridge

CAN

Motor Control

PWM

DAC

CTMU

ETH

Note: This diagram is provided as a general example. Please refer to the “Device

Overview” chapter in the specific device data sheet to determine availability of

Section 50. CPU for Devices with MIPS32® microAp-

The peripherals of a PIC32 device connect to the CPU through a System Bus and a series of

internal busses. The main peripheral bus connects most of the peripheral units to the System Bus

through one or more peripheral bridges.

The PIC32 CPU performs operations under program control. Instructions are fetched by the CPU

and are synchronously decoded and executed. Instructions exist in either Program Flash

memory or Data RAM memory. In addition, PIC32 devices with the microAptiv and M-Class core

incorporate the MIPS DSP Application-Specific Extension Revision 2 that provides digital signal

processing (DSP) capabilities with support for a number of powerful data processing operations.

The PIC32 CPU is based on a load/store architecture and performs most operations on a set of

internal registers. Specific load and store instructions are used to move data between these

internal registers and the outside world.

Figure 50-2: microAptiv™ Microprocessor Core Block Diagram

System

Coprocessor

MDU

(Enhanced MDU with

DSP ASE(3))

L1 Data

Cache(2)

MMU

(FMT or

TLB(1))

TAP

EJTAG

Power

Management

Off-Chip

Debug I/F

Execution Core

(RF/ALU/Shift, DSP ASE(3))

On-Chip

Memory

Trace

Off-Chip

Trace I/F

Memory

Interface Dual Memory

I/F

Note 1: TLB is available only on devices with the MPU Microprocessor core.

2: Level One (L1) caches are available only on devices with the MPU Microprocessor core.

3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet to determine

availability.

Instruction

Cache(2)

PIC32 Family Reference Manual

Figure 50-3: M-Class Microprocessor Core Block Diagram

Note 1: TLB is available only on devices with the MPU Microprocessor core.

2: Level One (L1) caches are available only on devices with the MPU Microprocessor core.

3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet to determine

availability.

System Bus

Execution Unit

ALU/Shift

Atomic/LdSt

DSP ASE(3)

System

Coprocessor

Enhanced MDU

(with DSP ASE(3))

GPR

(8 sets)

Debug/Profiling

Break Points

iFlowtrace®

Fast Debug Channel

Performance Counters

Sampling

Secure Debug

microMIPS™ I-Cache

Controller

MMU

(TLB)(1)

D-Cache

Controller

Power

M5150 Microprocessor Core

System

Interface

Interrupt

Interface

I-Cache(2)

D-Cache(2)

BIU

Decode

(MIPS32®/microMIPS™)

EJTAG

2-wire Debug

Management

PBCLK7

FPU

(Single & Double)

Section 50. CPU for Devices with MIPS32® microAp-

50.2.1 Busses

All PIC32 devices use a System Bus to connect the CPU and other bus masters to memory and

other target devices. The System Bus controls and arbitrates accesses between different bus

masters and targets. The type of System Bus and the bus architecture in a specific PIC32 device

is dependent on which the microAptiv or M-Class CPU core is used.

PIC32 devices based on the MCU Microprocessor core use a split-bus CPU architecture. In this

architecture, there are separate busses for instruction fetch and data load/store operations. Both

the instruction, or I-side bus, and the data, or D-side bus, are connected to the System Bus. The

System Bus allows simultaneous accesses between different bus masters accessing different

targets, and uses an arbitration algorithm to serialize accesses from different masters to the

same target. Since the CPU has two different data paths to the System Bus, the CPU is effec-

tively two different bus masters to the system. When running from Flash memory, load and store

operations to SRAM and the internal peripherals will occur in parallel to instruction fetches from

Flash memory.

PIC32 devices based on the MPU core use a unified bus CPU architecture along with a

multi-layer (crossbar) System Bus. In this architecture, the CPU has a single interface to the Sys-

tem Bus. The System Bus uses dedicated links to provide multiple independent data paths

between bus initiators and targets. This allows for concurrent data transactions on the bus.

In addition to the CPU, and depending on the device variant, there are other bus masters in

PIC32 devices:

• DMA controller

• In-Circuit Debugger (ICD)

• USB controller

• CAN controller

• Ethernet controller

50.2.2 Core Timer

The PIC32 architecture includes a core timer that is available to application programs. This timer

is implemented in the form of two coprocessor registers: the Count register, and the Compare

incrementing of Count can be optionally suspended during Debug mode. The Compare register

is used to cause a timer interrupt if desired. An interrupt is generated when the Compare register

matches the Count register. An interrupt is taken only if it is enabled in the interrupt controller.

For more information on the core timer, refer to 50.13 “Coprocessor 0 (CP0) Registers” and

Section 8. “Interrupts.” (DS60001108) of the “PIC32 Family Reference Manual”.

Note: Please refer to the “Memory Organization” chapter in the specific device data

sheet and Section 3. “Memory Organization” (DS60001115) of the “PIC32 Family

Reference Manual” for a description of the System Bus for a specific device.

PIC32 Family Reference Manual

50.3 PIC32 CPU DETAILS

50.3.1 Pipeline Stages

The pipeline consists of these five stages:

• Instruction (I) Stage

• Execution (E) Stage

• Memory (M) Stage

• Align (A) Stage

• Writeback (W) Stage

50.3.1.1 I STAGE – INSTRUCTION FETCH

During I stage:

• An instruction is fetched from the instruction SRAM

• microMIPS instructions are converted into instructions that are similar to MIPS32 instructions

50.3.1.2 E STAGE – EXECUTION

During E stage:

• Operands are fetched from the register file

• Operands from the M and A stage are bypassed to this stage

• The Arithmetic Logic Unit (ALU) begins the arithmetic or logical operation for

• The ALU calculates the data virtual address for load and store instructions and the MMU

performs the fixed virtual-to-physical address translation

• The ALU determines whether the branch condition is true and calculates the virtual branch

target address for branch instructions

• Instruction logic selects an instruction address and the MMU performs the fixed

virtual-to-physical address translation

• All multiply divide operations begin in this stage

50.3.1.3 M STAGE – MEMORY FETCH

During M stage:

• The arithmetic or logic ALU operation completes

• The data SRAM access is performed for load and store instructions

• A 16 x 16 or 32 x 16 MUL operation completes in the array and stalls for one clock in the M

stage to complete the carry-propagate-add in the M stage

• A 32 x 32 MUL operation stalls for two clocks in the M stage to complete the second cycle

of the array and the carry-propagate-add in the M stage

• Multiply and divide calculations proceed in the MDU. If the calculation completes before the

IU moves the instruction past the M stage, the MDU holds the result in a temporary register

until the IU moves the instructions to the A stage (and it is consequently known that it will

not be killed).

50.3.1.4 A STAGE – ALIGN

During A stage:

• A separate aligner aligns loaded data with its word boundary

• A MUL operation makes the result available for writeback. The actual register writeback is

performed in the W stage

• From this stage, load data or a result from the MDU are available in the E stage for

bypassing

50.3.1.5 W STAGE – WRITEBACK

During W stage:

Section 50. CPU for Devices with MIPS32® microAp-

For register-to-register or load instructions, the result is written back to the register file.

The microprocessor cores implement a “bypass” mechanism that allows the result of an

operation to be sent directly to the instruction that needs it without having to write the result to

the register, and then read it back.

Figure 50-4: Simplified PIC32 CPU Pipeline

The results of using instruction pipelining in the PIC32 core is a fast, single-cycle instruction

execution environment.

Figure 50-5: Single-Cycle Execution Throughput

I Stage E Stage M Stage

A to E Bypass

M to E Bypass

A Stage W Stage

Load Data, HI/LO Data

or CP0 Data

ALU

MStage

ALU

EStage

Bypass

Multiplexers

Rt Read

Rd Write

Reg File

Rt Address

Rs Read

Rs Address

Instruction

EI M A W

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

PIC32 Family Reference Manual

50.3.2 Execution Unit

The PIC32 Execution Unit is responsible for carrying out the processing of most of the instruc-

tions of the MIPS instruction set. The Execution Unit provides single-cycle throughput for most

instructions by means of pipelined execution. Pipelined execution, sometimes referred to as

“pipelining”, is where complex operations are broken into smaller pieces called stages. Operation

stages are executed over multiple clock cycles.

The Execution Unit contains the following features:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction address

• Logic for branch determination and branch target address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when executing instructions streams where data

producing instructions are followed closely by consumers of their results

• Leading Zero/One detect unit for implementing the CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bit-wise logical operations

• Shifter and Store Aligner

50.3.3 Multiply/Divide Unit (MDU)

The Multiply/Divide unit (MDU) performs multiply and divide operations. The MDU consists of a

32 x 16 multiplier, result-accumulation registers (HI and LO), multiply and divide state machines,

and all multiplexers and control logic required to perform these functions. The high-performance,

pipelined MDU supports execution of a 16 x 16 or 32 x 16 multiply operation every clock cycle;

32 × 32 multiply operations can be issued every other clock cycle. Appropriate interlocks are

implemented to stall the issue of back-to-back 32 x 32 multiply operations. Divide operations are

implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in the

worst case to complete. Any attempt to issue a subsequent MDU instruction while a divide is still

active causes a pipeline stall until the divide operation is completed.

The microprocessor cores implement an additional multiply instruction, MUL, which specifies that

lower 32-bits of the multiply result be placed in the register file instead of the HI/LO register pair.

By avoiding the explicit move from the LO (MFLO) instruction, which required when using the LO

operations is increased. Two instructions, multiply-add (MADD/MADDU) and multiply-subtract

( /MSUB MSUBU), are used to perform the multiply-add and multiply-subtract operations. The MADD

instruction multiplies two numbers, and then adds the product to the current contents of the HI

and LO registers. Similarly, the MSUB instruction multiplies two operands, and then subtracts the

product from the HI and LO registers. The MADD MADDU/ and MSUB MSUBU/ operations are

commonly used in Digital Signal Processor (DSP) algorithms.

The MDU is a separate pipeline for integer multiply and divide operations and DSP ASE multiply

instructions (see Note). This pipeline operates in parallel with the integer unit (IU) pipeline and

does not stall when the IU pipeline stalls. This allows the long-running MDU operations to be

partially masked by system sta instructions. The MDU supportslls and/or other integer unit

execution of one 32 x 32 multiply or multiply-accumulate operation every clock cycle. The 32-bit

divide operation executes in 12-38 clock cycles. The MDU also implements various shift

instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE.

50.3.4 Shadow Register Sets

The PIC32 processor implements one or more copies of the General Purpose Registers (GPR)

for use by high-priority interrupts. The extra banks of registers are known as shadow register

sets. When a high-priority interrupt occurs, the processor automatically switches to a shadow

reduces effective latency.

The shadow register sets are controlled by registers located in the System Coprocessor (CP0)

as well as the interrupt controller hardware located outside of the CPU core.

For more information on shadow register sets, refer to Section 8. “Interrupts” (DS60001108) of

the “PIC32 Family Reference Manual”.

Note: DSP ASE is not available on all devices. Refer to the “CPU” chapter of the specific

device data sheet to determine availability

Section 50. CPU for Devices with MIPS32® microAp-

50.3.5 Pipeline Interlock Handling

Smooth pipeline flow is interrupted when an instruction in a pipeline stage cannot advance due

to a data dependency or a similar external condition. Pipeline interruptions are handled entirely

in hardware. These dependencies are referred to as “interlocks”. At each cycle, interlock

conditions are checked for all active instructions. An instruction that depends on the result of a

previous instruction is an example of an interlock condition.

In general, MIPS processors support two types of hardware interlocks:

• Stalls – These interlocks are resolved by halting the entire pipeline. All instructions, cur-

rently executing in each pipeline stage, are affected by a stall.

• Slips – These interlocks allow one part of the pipeline to advance while another part of the

pipeline is held static

In the PIC32 processor core, all interlocks are handled as slips. These slips are minimized by

grabbing results from other pipeline stages by using a method called register bypassing, which

is described in 50.3.6 “Register Bypassing”.

As shown in Figure 50-6, the sub instruction has a source operand dependency on register r3

with the previous add instruction. The sub instruction slips by two clocks waiting until the result

of the add is written back to register r3. This slipping does not occur on the PIC32 family of

processors.

Figure 50-6: Pipeline Slip (If Bypassing Was Not Implemented)

Note: To illustrate the concept of a pipeline slip, the example in Figure 50-6 shows would

happen if the PIC32 core did not implement register bypassing.

EI M W

ESLIPI M A WE

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

ESLIP

Add r3, r2, r1

(r r r3 2 + 1

Sub r4, r3, r7

(r r r4 3 – 7

PIC32 Family Reference Manual

50.3.6 Register Bypassing

As mentioned previously, the PIC32 processor implements a mechanism called register bypass-

ing that helps reduce pipeline slips during execution. When an instruction is in the E stage of the

pipeline, the operands must be available for that instruction to continue. If an instruction has a

source operand that is computed from another instruction in the execution pipeline, register

bypassing allows a shortcut to get the source operands directly from the pipeline. An instruction

in the E stage can retrieve a source operand from another instruction that is executing in either

the M stage or the A stage of the pipeline. As seen in Figure 50-7, a sequence of three instruc-

tions with interdependencies does not slip at all during execution. This example uses both A to

E, and M to E register bypassing. Figure 50-8 shows the operation of a load instruction utilizing

A to E bypassing. Since the result of load instructions are not available until the A pipeline stage,

M to E bypassing is not needed.

The performance benefit of register bypassing is that instruction throughput is increased to the

rate of one instruction per clock for ALU operations, even in the presence of register

dependencies.

Figure 50-7: IU Pipeline M to E Bypass

Figure 50-8: IU Pipeline A to E Data Bypass

EI M W

EI WA

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

Add1

r r r3 = 2 + 1

Sub2

r r r4 = 3 – 7

Add3

r r r5 = 3 + 4 EI AM

M to E Bypass A to E Bypass

M to E Bypass

EI M W

EI WA

One

Cycle One

Cycle

Load Instruction

Consumer of Load Data Instruction EI AM

Data Bypass from A to E

One Clock

Load Delay

Section 50. CPU for Devices with MIPS32® microAp-

50.4 SPECIAL CONSIDERATIONS WHEN WRITING TO CP0 REGISTERS

In general, the PIC32 core ensures that instructions are executed following a fully sequential pro-

gram model. Each instruction in the program sees the results of the previous instruction. There

are some deviations to this model. These deviations are referred to as “hazards”.

In privileged software, there are two hazards:

• Execution

• Instruction

50.4.1 Execution Hazards

Execution hazards are those created by the execution of one instruction, and seen by the

execution of another instruction. Table 50-2 lists the execution hazards.

Table 50-2: Execution Hazards

50.4.2 Instruction Hazards

Instruction hazards are those created by the execution of one instruction, and seen by the

instruction fetch of another instruction. Table 50-3 lists the instruction hazards.

Table 50-3: Instruction Hazards

Created by Seen by Hazard On Spacing

(Instructions)

LL MFC0 LLAddr 1

MTC0 Coprocessor instruction execution

depends on the new value of the CU0 bit

(Status[28])

CU0 bit (Status[28]) 1

MTC0 ERET EPC, DEPC, ErrorEPC 1

MTC0 DI, EI, Interrupted Instruction IE bit (Status[0]) 1

MTC0 Interrupted Instruction IP1 and IP0 bits (Cause[1] and [0]) 3

MTC0 TLBR TLBWI TLBWR, , EntryHi 1

MTC0 TLBP, Load/Store affected by new state ASID[7:0] bits (EntryHi[7:0]) 1

MTC0 TLBWI TLBWR, Index 1

MTC0 RDPGPR WRPGPR, PSS[3:0] bits (SRSCtl[9:6]) 1

MTC0 Instruction is not seeing a core timer

interrupt

Compare update that clears the core

timer Interrupt

MTC0 Instruction affected by change Any other CP0 register 2

Created by Seen by Hazard On Spacing

(Instructions)

TLBWR TLBWI, Instruction fetch using new TLB entry TLB entry 3

MTC0 Instruction fetch seeing the new value

(including a change to ERL followed by an

instruction fetch from the useg segment)

Status

MTCO Instruction fetch seeing the new value ASID[7:0] bits (EntryHi[7:0]) 3

MTC0 Instruction fetch seeing the new value WatchHi and WatchLo 1

MTC0 Interrupted instruction IP1 and IP0 bits

(Cause[1] and [0])

Instruction

stream write via

cache

Instruction fetch seeing the new instruction

stream

Cache entries 3

Instruction

stream write via

store

Instruction fetch seeing the new instruction

stream

Cache entries System

dependent

PIC32 Family Reference Manual

50.5 MIPS32 ARCHITECTURE

The MIPS32 architecture is based on a fixed-length, regularly encoded instruction set and uses

a load/store data model. The architecture is streamlined to support optimized execution of

high-level languages. Arithmetic and logic operations use a three-operand format, allowing

compilers to optimize complex expressions formulation. Availability of 32 general-purpose

registers enables compilers to further optimize code generation for performance by keeping

frequently accessed data in registers.

For more information and documentation, refer to the MIPS32 Architecture web page at:

http://www.imgtec.com/mips/architectures/mips32.asp

50.5.1 Architecture Release 2

PIC32 devices with the microAptiv core utilize Release 2 of the MIPS32 processor architecture,

and implement the following features:

• Vectored interrupts using and external-to-core interrupt controller, which provides the ability

to vector interrupts directly to a handler for that interrupt

• Programmable exception vector base, which allows the base address of the exception

vectors to be moved for exceptions that occur when Status

BEV is ‘0’. This feature enables

any system to place the exception vectors in memory that is appropriate to the system

environment.

• Atomic interrupt enable/disable, which includes two added instructions to atomically enable

or disable interrupts, and return the previous value of the Status register

• The ability to disable the Count register for highly power-sensitive applications

• GPR shadow registers, which provide the addition of GPR shadow registers and the ability

to bind these registers to a vectored interrupt or exception

• Field, Rotate, and Shuffle instructions, which add additional capability in processing bit

fields in registers

• Explicit hazard management, which provides a set of instructions to explicitly manage

hazards, in place of the cycle-based SSNOP method of dealing with hazards

50.5.2 Architecture Release 5

PIC32 devices with the M-Class core utilize all of the features of Release 2, as well as the

following Release 5 features:

• User mode access through the UFR bit in the Config5 Register (CP0 Register 16, Select 5)

• Additional MCU ASE instructions: ASET and ACLR for setting and clearing atomic 8-bit

memory locations

Section 50. CPU for Devices with MIPS32® microAp-

50.6 CPU BUS

The PIC32 devices use two different CPU bus architectures, either split-bus or data/instruction

bus, depending on which CPU core is implemented.

50.6.1 Split-bus Architecture

PIC32 devices based on the MCU Microprocessor core have a Split-bus architecture, with two

distinct busses to provide parallel instruction and data operations. Load and store operations

occur simultaneously as instruction fetches. The two busses are known as the I-side bus, which

is used for feeding instructions into the CPU, and the D-side bus, which is used for data transfers.

In the split-bus architecture, the CPU fetches instructions during the I-pipeline stage. A fetch is

issued to the I-side bus and is handled by the System Bus. Depending on the address, the

System Bus will do one of the following:

• Forward the fetch request to the Prefetch Cache unit (if available)

• Forward the fetch request to the DRM unit, or

• Cause an exception

Instruction fetches always use the I-side bus independent of the addresses being fetched.

The D-side bus processes all load and store operations executed by the CPU. When a load or

store instruction is executed, the request is routed to the System Bus by the D-side bus. This

operation occurs during the M-pipeline stage and is routed to one of several targets:

• Data RAM

• Prefetch Cache/Flash memory

• Fast Peripheral Bus (Interrupt controller, DMA, Debug unit, USB, Ethernet, GPIO ports)

• General Peripheral Bus (UART, SPI, Flash Controller, EPMP/EPSP, TRCC Timers, Input

Capture, PWM/Output Compare, ADC, Dual Compare, I2C, Clock SIB, and Reset SIB)

50.6.2 Data/Instruction Architecture

PIC32 devices based on the MPU core have a unified Data or Instruction bus connected to the

System Bus. This architecture uses a multi-layer System Bus to provide multiple simultaneous

data transactions between bus initiators and targets.

50.7 INTERNAL SYSTEM BUSSES

The internal busses of the PIC32 processor connect the peripherals to the System Bus. The

System Bus routes bus accesses from different initiators to a set of targets utilizing several data

paths throughout the device to help eliminate performance bottlenecks.

Some of the paths that the System Bus uses serve a dedicated purpose, while others are shared

between several targets.

The data RAM and Flash memory read paths are dedicated paths, allowing low-latency access

to the memory resources without being delayed by peripheral bus activity. The high-bandwidth

peripherals are placed on a high-speed bus. These include the Interrupt controller, Debug unit,

DMA engine, the USB Host/Peripheral unit, and other high-bandwidth peripherals (i.e., CAN,

Ethernet engines).

Peripherals that do not require high-bandwidth are located on a separate peripheral bus to save

power.

PIC32 Family Reference Manual

50.8 SET/CLEAR/INVERT

To provide single-cycle bit operations on peripherals, the registers in the peripheral units can be

accessed in three different ways depending on peripheral addresses. Each register has four dif-

ferent addresses. Although the four different addresses appear as different registers, they are

really just four different methods to address the same physical register.

Figure 50-9: Four Addresses for a Single Physical Register

The base register address provides normal Read/Write access, while the other three provide

special write-only functions.

• Normal access

• Set bit atomic RMW access

• Clear bit atomic RMW access

• Invert bit atomic RMW access

Peripheral reads must occur from the base address of each peripheral register. Reading from a

Set/Clear/Invert address has an undefined meaning, and may be different for each peripheral.

Writing to the base address writes an entire value to the peripheral register. All bits are written.

For example, assume a register contains 0xAAAA5555 before a write of 0x000000FF. After the

write, the register will contain 0x000000FF (assuming that all bits are R/W bits).

Writing to the Set address for any peripheral register causes only the bits written as ‘1’s to be set

in the destination register. For example, assume that a register contains 0xAAAA5555 before a

write of 0x000000FF to the set register address. After the write to the Set register address, the

value of the peripheral register will contain 0xAAAA55FF.

Writing to the Clear address for any peripheral register causes only the bits written as ‘1’s to be

cleared to ‘0’s in the destination register. For example, assume that a register contains

0xAAAA5555 before a write of 0x000000FF to the Clear register address. After the write to the

Clear register a e peripheral register will contain 0xAAAA5500.ddress, the value of th

Writing to the Invert address for any peripheral register causes only the bits written as ‘1’s to be

inverted, or toggled, in the destination register. For example, assume that a register contains

0xAAAA5555 before a write of 0x000000FF to the invert register address. After the write to the

Invert register, the value of the peripheral register will contain 0xAAAA55AA.

50.9 ALU STATUS BITS

Unlike most other PIC microcontrollers, the PIC32 processor does not use Status register flags.

Condition flags are used on many processors to help perform decision making operations during

program execution. Flags are set based on the results of comparison operations or some arith-

metic operations. Conditional branch instructions on these machines then make decisions based

on the values of the single set of condition codes.

Instead, the PIC32 processor uses instructions that perform a comparison and stores a flag or

value into a General Purpose Register. A conditional branch is then executed with this general

purpose register used as an operand.

Peripheral RegisterRegister Address

Clear Bits

Set Bits

Invert Bits

Section 50. CPU for Devices with MIPS32® microAp-

50.10 INTERRUPT AND EXCEPTION MECHANISM

The PIC32 family of processors implement an efficient and flexible interrupt and exception han-

dling mechanism. Interrupts and exceptions both behave similarly in that the current instruction

flow is changed temporarily to execute special procedures to handle an interrupt or exception.

The difference between the two is that interrupts are usually a result of normal operation, and

exceptions are a result of error conditions such as bus errors.

When an interrupt or exception occurs, the processor does the following:

1. The PC of the next instruction to execute after the handler returns is saved into a

coprocessor register.

2. The Cause register is updated to reflect the reason for exception or interrupt.

3. The Status register EXL or ERL bit is set to cause Kernel mode execution.

4. Handler PC is calculated from Ebase and OFFSET values.

5. Automated Interrupt Epilogue can save some of the COP0 state in the stack and

automatically update some of the COP0 registers in preparation for interrupt handling.

6. Processor starts execution from new PC.

This is a simplified overview of the interrupt and exception mechanism. Refer to the “CPU

Exceptions and Interrupt Controller” chapter in the specific device data sheet for details.

50.11 PROGRAMMING MODEL

The PIC32 family of processors is designed to be used with a high-level language such as the C

programming language. It supports several data types and uses simple but flexible addressing

modes needed for a high-level language. There are 32 General Purpose Registers and two

special registers for multiplying and dividing.

There are three different formats for the machine language instructions on the PIC32 processor:

• Immediate or I-type CPU instructions

• Jump or J-type CPU instructions, and

• Registered or R-type CPU instructions

Most operations are performed in registers. The register type CPU instructions have three

operands; two source operands and a destination operand.

Having three operands and a large register set allows assembly language programmers and

compilers to use the CPU resources efficiently. This creates faster and smaller programs by

allowing intermediate results to stay in registers rather than constantly moving data to and from

memory.

The immediate format instructions have an immediate operand, a source operand and a desti-

nation operand. The jump instructions have a 26-bit relative instruction offset field that is used to

calculate the jump destination.

Note: In this section, the terms “precise” and “imprecise” are used to describe exceptions.

A precise exception is one in which the EPC (CP0, Register 14, Select 0) can be

used to identify the instruction that caused the exception. For imprecise exceptions,

the instruction that caused the exception cannot be identified. Most exceptions are

precise. Bus error exceptions may be imprecise.

PIC32 Family Reference Manual

50.11.1 CPU Instruction Formats

A CPU instruction is a single 32-bit aligned word. The CPU instruction formats are:

• Immediate (see Figure 50-10)

• Jump (see Figure 50-11)

• Register (see Figure 50-12)

Table 50-4 describes the fields used in these instructions.

Table 50-4: CPU Instruction Format Fields

Figure 50-10: Immediate (I-Type) CPU Instruction Format

Figure 50-11: Jump (J-Type) CPU Instruction Format

Figure 50-12: Register (R-Type) CPU Instruction Format

Field Description

opcode 6-bit primary operation code.

rd 5-bit specifier for the destination register.

rs 5-bit specifier for the source register.

rt 5-bit specifier for the target (source/destination) register or used to specify

functions within the primary opcode REGIMM.

immediate 16-bit signed immediate used for logical operands, arithmetic signed operands,

load/store address byte offsets, and PC-relative branch signed instruction

displacement.

instr_index 26-bit index shifted left two bits to supply the low-order 28 bits of the jump

target address.

sa 5-bit shift amount.

function 6-bit function field used to specify functions within the primary opcode

SPECIAL.

31 26 25 21 20 16 15 0

opcode rs rt immediate

6 5 5 16

31 26 25 21 20 16 15 11 10 6 5 0

opcode instr_index

6 26

31 26 25 21 20 16 15 11 10 6 5 0

opcode rs rt rd sa function

6 5 5 5 5 6

Section 50. CPU for Devices with MIPS32® microAp-

50.11.2 CPU Registers

The PIC32 architecture defines the following CPU registers:

• Thirty-two 32-bit General Purpose Registers (GPRs)

• The standard MIPS32 architecture defines one pair of HI/LO accumulator registers (AC0).

The cores in PIC32 devices include the DSP ASE (see Note), which provides three addi-

tional pairs of HI/LO accumulator registers (AC1, AC2, and AC3). These registers improve

the parallelization of independent accumulation routines. DSP instructions that target the

accumulators use two instruction bits to specify the destination accumulator.

• A special purpose program counter (PC), which is affected only indirectly by certain

instructions; it is not an architecturally visible register.

50.11.2.1 CPU GENERAL PURPOSE REGISTERS

Two of the CPU General Purpose Registers have assigned functions:

• r0 – This register is hard-wired to a value of ‘0’, and can be used as the target register for

any instruction the result of which will be discarded. r0 can also be used as a source when

a ‘0’ value is needed.

• r31 – This is the destination register used by JAL, BLTZAL, BLTZALL, BGEZAL, and

BGEZALL, without being explicitly specified in the instruction word; otherwise, r31 is used

as a normal register.

The remaining registers are available for general purpose use.

50.11.2.2 REGISTER CONVENTIONS

Although most of the registers in the PIC32 architecture are designated as General Purpose

Registers, as shown in Table 50-5, there are some recommended uses of the registers for correct

software operation with high-level languages such as the Microchip MPLAB

® XC32 C/C++

compiler.

Table 50-5: Register Conventions

Note: DSP ASE is not available on all devices. Please consult the “CPU” chapter of the

specific device data sheet to determine availability

CPU

Symbolic

r0 zero Always ‘0’ (see Note 1)

r1 at Assembler Temporary

r2 - r3 v0-v1 Function Return Values

r4 - r7 a0-a3 Function Arguments

r8 - r15 t0-t7 Temporary – Caller does not need to preserve contents

r16 - r23 s0-s7 Saved Temporary – Caller must preserve contents

r24 - r25 t8-t9 Temporary – Caller does not need to preserve contents

r26 - r27 k0-k1 Kernel temporary – Used for interrupt and exception handling

r28 gp Global Pointer – Used for fast-access common data

r29 sp Stack Pointer – Software stack

r30 s8 or fp Saved Temporary – Caller must preserve contents OR

Frame Pointer – Pointer to procedure frame on stack

r31 ra Return Address (see Note 1)

Note 1: Hardware enforced, not just convention.

PIC32 Family Reference Manual

50.11.2.3 CPU SPECIAL PURPOSE REGISTERS

The CPU contains these special purpose registers:

• PC – Program Counter register

• AC0 through AC3 – 64-bit Accumulator register pairs (HI/LO):

- HI/LO – Multiply and divide register pair (high and low result):

• During a multiply operation, the HI and LO registers store the product of integer multiply

• During a multiply-add or multiply-subtract operation, the HI and LO registers store the

result of the integer multiply-add or multiply-subtract

• During a division, the HI and LO registers store the quotient (in LO) and remainder (in

HI) of integer divide

• During a multiply-accumulate, the HI and LO registers store the accumulated result of

the operation

Figure 50-13 shows the layout of the CPU registers.

Figure 50-13: CPU Registers

31 0 31 0

r0 (zero) HI (0)

r1 (at) LO (0)

r2 (v0) HI (1)

r3 (v1) LO (1)

r4 (a0) HI (2)

r5 (a1) LO (2)

r6 (a2) HI (3)

r7 (a3) LO (3)

r8 (t0)

r9 (t1)

r10 (t2)

r11 (t3)

r12 (t4)

r13 (t5)

r14 (t6)

r15 (t7)

r16 (s0)

r17 (s1)

r18 (s2)

r19 (s3)

r20 (s4)

r21 (s5)

r22 (s6)

r23 (s7)

r24 (t8)

r25 (t9)

r26 (k0)

r27 (k1)

r28 (gp)

r29 (sp)

r30 (s8 or fp) 31 0

r31 (ra) PC

General Purpose Registers Special Purpose Registers

Section 50. CPU for Devices with MIPS32® microAp-

Table 50-6: microMIPS 16-bit Instruction Register Usage

Table 50-7: microMIPS Special Registers

16-bit

Encoding

32-bit MIPS

Encoding

Symbolic

Name Description

0 16/0 s0/zero General-purpose register

1 17 s1 General-purpose register

2 2 v0 General-purpose register

3 3 v1 General-purpose register

4 4 a0 General-purpose register

5 5 a1 General-purpose register

6 6 a2 General-purpose register

7 7 a3 General-purpose register

N/A 28 gp microMIPS implicitly referenced

General-pointer register

N/A 29 sp microMIPS implicitly referenced Stack

pointer register

N/A 31 ra microMIPS implicitly referenced Return

address register

Symbolic

Name Purpose

PC Program counter. The PC-relative instructions can access this register as an

operand.

HI Contains high-order word of multiply or divide result.

LO Contains low-order word of multiply or divide result.

PIC32 Family Reference Manual

50.11.3 How to Implement Stack/MIPS Calling Conventions

The PIC32 CPU does not have hardware stacks. Instead, the processor relies on software to pro-

vide this functionality. Since the hardware does not perform stack operations itself, a convention

must exist for all software within a system to use the same mechanism. For example, a stack can

grow either toward lower addresses, or grow toward higher addresses. If one piece of software

assumes that the stack grows toward a lower address, and calls a routine that assumes that the

stack grows toward a higher address, the stack would become corrupted.

Using a system-wide calling convention prevents this problem from occurring. The Microchip

MPLAB® XC32 C/C++ Compiler assumes the stack grows toward lower addresses.

50.11.4 Processor Modes

There are two operational modes and one special mode of execution in the PIC32 family CPUs:

User mode, Kernel mode and Debug mode. The processor starts execution in Kernel mode, and

if desired, can stay in Kernel mode for normal operation. User mode is an optional mode that

allows a system designer to partition code between privileged and unprivileged software. Debug

mode is normally only used by a debugger or monitor.

One of the main differences between the modes of operation is the memory addresses that soft-

ware is allowed to access. Peripherals are not accessible in User mode. Figure 50-14 shows the

different memory maps for each mode. For more information on the processor’s memory map,

refer to Section 3. “Memory Organization” (DS60001115) of the “PIC32 Family Reference

Manual”.

Figure 50-14: CPU Modes

useg kuseg kuseg

kseg0

kseg1

kseg2

kseg3

kseg2

kseg1

kseg0

kseg3

dseg

User Mode Kernel Mode Debug ModeVirtual Address

0x7FFF_FFFF

0x8000_0000

0x9FFF_FFFF

0xBFFF_FFFF

0xDFFF_FFFF

0xFF1F_FFFF

0xFF3F_FFFF

0xFFFF_FFFF

0xA000_0000

0xC000_0000

0xE000_0000

0xFF20_0000

0xFF40_0000

0x0000_0000

Section 50. CPU for Devices with MIPS32® microAp-

50.11.4.1 KERNEL MODE

To access many of the hardware resources, the processor must be operating in Kernel mode.

Kernel mode gives software access to the entire address space of the processor as well as

access to privileged instructions.

The processor operates in Kernel mode when the DM bit in the Debug register is ‘0’ and the Status

• UM = 0

• ERL = 1

• EXL = 1

When a non-debug exception is detected, EXL or ERL will be set and the processor will enter

Kernel mode. At the end of the exception handler routine, an Exception Return (ERET) instruction

is generally executed. The ERET instruction jumps to the Exception PC (EPC or ErrorPC

depending on the exception), clears ERL, and clears EXL if ERL= 0.

If UM = 1 the processor will return to User mode after returning from the exception when ERL

and EXL are cleared back to ‘0’.

50.11.4.2 USER MODE

When executing in User mode, software is restricted to use a subset of the processor’s

resources. In many cases it is desirable to keep application-level code running in User mode

where if an error occurs it can be contained and not be allowed to affect the Kernel mode code.

Applications can access Kernel mode functions through controlled interfaces such as the

SYSCALL mechanism.

As seen in Figure 50-14, User mode software has access to the USEG memory area.

To operate in User mode, the Status register must contain each the following bit values:

• UM = 1

• EXL = 0

• ERL = 0

50.11.4.3 DEBUG MODE

Debug mode is a special mode of the processor normally only used by debuggers and system

monitors. Debug mode is entered through a debug exception and has access to all Kernel mode

resources as well as special hardware resources used to debug applications.

The processor is in Debug mode when the DM bit in the Debug register is ‘1’.

Debug mode is normally exited by executing a DERET instruction from the debug handler.

PIC32 Family Reference Manual

50.12 FLOATING POINT UNIT (FPU)

PIC32 devices with the M-Class core contain a Floating Point Unit (FPU) that implements the

MIPS Release 5 Instruction Set Architecture for floating point computation.

50.12.1 Features

Some of the most important features of this module include:

• The PIC32 implementation supports the “IEEE Standard for Binary Floating-Point

Arithmetic” (ANSI/IEEE 754 Standard) for single and double precision data formats. See

50.12.6.5 “IEEE 754-1985 Standard” for more information.

• Full 64-bit operation is implemented in both the register file and functional units. The FPU

has 32 64-bit floating point registers used for all of the floating point operations.

• A 32-bit Floating Point Control Register controls the operation of the FPU, and monitors

condition codes and exception conditions

• The performance of the unit is optimized for single precision formats. Most instructions have

one FPU cycle throughput and four FPU cycle latency.

• The FPU implements compound multiply-add (MADD) and multiply-sub (MSUB) instructions

with intermediate rounding after the multiply function. The result is guaranteed to be the

same as executing a MUL followed by an ADD SUB/ instruction, but the instruction latency,

instruction fetch, dispatch bandwidth, and the total number of register accesses is improved.

• IEEE denormalized input operands and results are supported by hardware for some

instructions. A fast flush-to-zero mode is provided to optimize performance for IEEE

denormalized results. The fast flush-to-zero mode has to be enabled through the FPU

control registers, and use of this mode is recommended for best performance when

denormalized results are generated.

• Additional arithmetic operations not specified by IEEE 754 Standard (for example, reciprocal

and reciprocal square root) are specified by the MIPS

® architecture (see Note) and are

implemented by the FPU. To achieve low latency counts, these instructions satisfy more

relaxed precision requirements.

• The MIPS FPU architecture is designed such that a combination of hardware and software

can be used to implement the architecture. The PIC32 FPU can operate on numbers within

a specific range (the IEEE normalized numbers), but it relies on a software handler to

operate on numbers not handled by the FPU hardware (the IEEE denormalized numbers).

• The FPU has a separate pipeline for floating point instruction execution. This pipeline

operates in parallel with the integer core pipeline and does not stall when the integer

pipeline stalls. This allows long-running FPU operations, such as divide or square root, to

be partially masked by system stalls and/or other integer unit instructions.

• The FPU access is provided through Coprocessor 1. Like the main processor core,

Coprocessor 1 is programmed and operated using a Load/Store instruction set. The

processor core communicates with Coprocessor 1 using a dedicated coprocessor interface.

The FPU functions as an autonomous unit. The hardware is completely interlocked such

that, when writing software, the programmer does not have to worry about inserting delay

slots after loads and between dependent instructions.

• Arithmetic instructions are always dispatched and completed in order, but loads and stores

can complete out of order. The exception model is ‘precise’ at all times.

Refer to 50.14 “Coprocessor 1 (CP1) Registers” for information on the related FPU registers.

Figure 50-15 shows a block diagram of the PIC32 FPU.

Note: This module is not available on all devices. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

Note: Refer to the Imagination Technologies Ltd. website, www.imgtec.com, for

information on the MIPS architecture.

Section 50. CPU for Devices with MIPS32® microAp-

Figure 50-15: FPU Block Diagram

50.12.2 FPU data formats

The FPU supports the single-precision and double-precision floating point data types as

specified by the IEEE 754 Standard.

In addition, fixed point data types are supported: signed integers that are provided by the MIPS

architecture.

50.12.2.1 FLOATING POINT FORMATS

The PIC32 FPU supports the following two floating point formats:

• a 32-bit single-precision floating point (type S, shown in Figure 50-16)

• a 64-bit double-precision floating point (type D, shown in Figure 50-17)

The single and double floating point data types are composed of three fields: sign, exponent,

fraction.

They represent numeric values as well as the following special entities:

• Two infinities: +∞ ∞ and -

• Signaling non-numbers (SNaNs)

• Quiet non-numbers (QNaNs)

• Numbers of the form: (-1)s 2E b0.b1 b2..bp-1, where:

- s = 0 or 1

- E = any integer between E_min and E_max, inclusive

- bi = 0 or 1 (the high bit, b0, is to the left of the binary point)

- p is the signed-magnitude precision

The sizes for the single and double precision numbers supported by the architecture are listed in

Table 50-8.

Processor

Core

Coprocessor

Interface

Control

Bypass

Add

Divide/ Multiply Load/Store

Square Root

PIC32 Family Reference Manual

Table 50-8: Parameters of Floating Point Data Types

Figure 50-16: Single-Precision Floating Point Format (S)

Figure 50-17: Double-Precision Floating Point Format (D)

The fields in the Figure 50-16 and Figure 50-16 are:

• 1-bit sign, S

• Biased exponent, e = E + bias

• Binary fraction, f =.b1 b2..bp-1 (the b0 bit is hidden; it is not recorded)

Values are encoded in the specified format using the unbiased exponent, fraction, and sign

values listed in Table 50-9.

The high-order bit of the Fraction field, identified as b1, has also special importance for NaNs.

Parameter Single Double

Bits of mantissa precision, p 24 53

Maximum exponent, E_max +127 +1023

Minimum exponent, E_min -126 -1022

Exponent bias +127 +1023

Bits in exponent field, e 8 11

Representation of b0 integer

bit

Hidden Hidden

Bits in fraction field, f 23 52

Total format width in bits 32 64

Magnitude of largest repre-

sentable number

3.4028234664e+38 1.7976931349e+308

Magnitude of smallest normal-

ized representable number

1.1754943508e-38 2.2250738585e-308

S Exponent [0:7] Fraction [0:22]

S Exponent [0:10] Fraction [0:51]

Section 50. CPU for Devices with MIPS32® microAp-

Table 50-9: Single or Double Floating Point Data Type Encoding

50.12.2.1.1Normalized and Denormalized Numbers

There is just one encoding for each nonzero numerical value that could be represented as a

single or double data type. This is called the normalized form.

The high-order bit of the p-bit mantissa, which lies to the left of the binary point, is “hidden,” and

not recorded in the Fraction field. The value of this bit can be determined by looking at the value

of the exponent:

• When the unbiased exponent is in the range E_min to E_max, inclusive, the number is

normalized and the hidden bit must be ‘1’.

• If the numeric value cannot be normalized because the exponent is less than E_min, the

representation is denormalized, the encoded number has an exponent of E_min – 1, and

the hidden bit has the value ‘0’.

Please note that plus and minus zero are special cases that are not regarded as denormalized

values.

50.12.2.1.2Infinity and NaNs

A floating point operation under certain conditions, such as not using initialized variables,

violations of mathematical rules, or results that cannot be represented, can signal exception

conditions that are part of the IEEE 754 Standard.

Usually a program will take a trap when an exception condition is encountered. However a

different approach is possible where a computation that encounters any of these conditions

proceeds without trapping, but generates a result indicating that an exceptional condition arose

during the computation. To allow this behavior each floating point format defines representations

for plus infinity (+∞ ∞), minus infinity (- ), quiet non-numbers (QNaN), and signaling non-numbers

(SNaN) as required by the IEEE 754 Standard. See Table 50-9 for these values.

Unbiased

Ef s b1 Value V Type of Value

Value of Typical

Single Bit Pattern

(see Note 1)

Value of Typical Double

Bit Pattern

E_max+1 ≠ 0 1 SNaN Signaling NaN

(FCSRNAN2008 = 0)

0x7FFFFFFF 0x7FFFFFFF FFFFFFFF

0 QNaN Quiet NaN

(FCSRNAN2008 = 0)

0x7FBFFFFF 0x7FF7FFFF FFFFFFFF

E_max+1 ≠ 0 1 QNaN Quiet NaN

(FCSRNAN2008 = 1)

0x7FFFFFFF 0x7FFFFFFF FFFFFFFF

0 SNaN Signaling NaN

(FCSRNAN2008 = 1)

0x7FBFFFFF 0x7FF7FFFF FFFFFFFF

E_max+1 0 1 -∞Minus infinity 0xFF800000 0xFFF00000 00000000

0 +∞Plus infinity 0x7F800000 0x7FF00000 00000000

E_max

E_min

1 -(2E)(1.f) Negative normalized

number

0x80800000

through

0xFF7FFFFF

0x80100000 00000000

through

0xFFEFFFFF FFFFFFFF

0 +(2E)(1.f) Positive normalized

number

0x00800000

through

0x7F7FFFFF

0x00100000 00000000

through

0x7FEFFFFF FFFFFFFF

E_min-1 ≠ 0 1 -(2E_min)(0.f) Negative denormalized

number

0x807FFFFF 0x800FFFFF FFFFFFFF

0 +(2E_min)(0.f) Positive denormalized

number

0x007FFFFF 0x000FFFFF FFFFFFFF

E_min-1 0 1 -0 Negative zero 0x80000000 0x80000000 00000000

0 +0 Positive zero 0x00000000 0x00000000 00000000

Note 1: The “Typical” nature of the bit patterns for the NaN and denormalized values reflects the fact that the sign

might have either value (NaN) and that the fraction field might have any non-zero value (both). As such,

the bit patterns shown are one value in a class of pot ent these special values.ential values that repres

PIC32 Family Reference Manual

50.12.2.2 INFINITY ARITHMETIC

Infinity represents a number with magnitude too large to be represented in the given format.

During a computation it represents a magnitude overflow. A correctly signed +∞ or -∞ will be

generated as the default result in division by zero operations and some cases of overflow as

described in 50.12.5 “Floating Point Exceptions Overview”.

When created as a default result, can become an operand in a subsequent operation. The∞

ordering is such that -∞ ∞ < (every finite number) < + . Arithmetic with ∞ is the limiting case of

real arithmetic with operands of arbitrarily large magnitude, when such limits exist. In these

cases, arithmetic on ∞ is regarded as exact, and exception conditions do not arise. The

out-of-range indication represented by ∞ is propagated through subsequent computations.

For some cases, there is no meaningful limiting case in real arithmetic for operands of

∞. These

cases raise the Invalid Operation exception condition as described in 50.12.3 “General Floating

Point Registers”.

50.12.2.2.1 Signaling Non-Number (SNaN)

SNaN operands cause an Invalid Operation exception for arithmetic operations. SNaNs are

useful values to put in uninitialized variables. A SNaN is never produced as a result value.

The MIPS architecture makes the formatted operand move instructions (MOV.fmt MOVT.fmt, ,

MOVF.fmt MOVN.fmt MOVZ.fmt, , ) non-arithmetic; they do not signal IEEE 754 Standard

exceptions.

50.12.2.2.2Quiet Non-Number (QNaN)

QNaNs provide diagnostic information propagated from invalid or unavailable data and results.

This propagation requires that the information contained in a QNaN be preserved through

arithmetic operations and floating point format conversions.

Arithmetic operations with QNaN operands do not signal an exception. When a floating point

result is to be delivered, a QNaN operand causes an arithmetic operation to supply a QNaN

result. When possible, this QNaN result is one of the operand QNaN values.

QNaNs have similar effects to SNaNs on operations that do not deliver a floating point result (i.e.,

comparison operations).

When certain invalid operations not involving QNaN operands are performed and the trap is not

enabled, a new QNaN value is created. Table 50-10 shows the QNaN value generated when no

input operand QNaN value can be copied. The values listed for the fixed point formats are the

values supplied to satisfy the IEEE 754 Standard when a QNaN or infinite floating point value is

converted to fixed point. There is no other feature of the architecture that detects or utilizes these

“integer QNaN” values.

Table 50-10: Value Supplied When a New QNaN is Created

50.12.2.3 FIXED POINT FORMATS

The PIC32 FPU provides two fixed point data types which are the signed integers that are

provided by the MIPS architecture:

• 32-bit Word Fixed Point Format (type W)

• 64-bit Long Word Fixed Point Format (type L)

The fixed point values are held in 2’s complement format, which is used for signed integers in the

CPU. Unsigned fixed point data types are not provided by the architecture; application software

can synthesize computations for unsigned integers from the existing instructions and data types.

Format New QNan Value

(FCSRNAN2008 = 0)

New QNaN Value

(FCSRNAN2008 = 1)

Single floating point 0x7FBF FFFF 0x7FFF FFFF

Double floating point 0x7FF7 FFFF FFFF FFFF 0x7FFF FFFF FFFF FFFF

Word fixed point 0x7FFF FFFF 0x7FFF FFFF

Long word fixed point 0x7FFF FFFF FFFF FFFF 0x7FFF FFFF FFFF FFFF

Section 50. CPU for Devices with MIPS32® microAp-

50.12.3 General Floating Point Registers

The FPU is a 64b floating point unit with 64-bit Floating Point General Registers (FPRs) but a

32b register mode for MIPS backwards compatibility is also supported. The FR bit (CP0[26]) in

the CP0 Status register determines which mode is selected:

• When the FR bit is a ‘1’, the FPU is in FR64 mode and the 64b register model is used,

which defines 32 64-bit registers with all formats supported in a register.

• When the FR bit is a ‘0’, the FPU is in FR32 mode and the 32b register model is used,

which defines 32 32-bit registers with double format values stored in even-odd pairs of

registers; The register file can also be viewed as having 16 64-bit registers. When

configured this way, there are several restrictions for double operations:

- Any double operations which specify an odd register as a source or destination will

cause a Reserved Instruction exception

- MTHC1/MFHC1 instructions which access an odd FPU register will signal a Reserved

Instruction exception.

50.12.3.1 FPR REGISTERS AND FORMATTED OPERAND LAYOUT

The FPU instructions that operate on formatted operand values specify the Floating Point

only half the space in an FPR. See for the FPR organization and

Figure 50-18 and Figure 50-19

the way that operand data is stored in them.

Figure 50-18: Single Floating Point or Word Fixed Point Operand in an FPR

Figure 50-19: Double Floating Point or Long Word Fixed Point Operand in an FPR

50.12.3.2 FORMATS OF VALUES USED IN FPR REGISTERS

Unlike the CPU, the FPU neither interprets the binary encoding of source operands nor produces

a binary encoding of results for every operation. The value held in a FPR has a format, or type,

and it can be used only by instructions that operate on that format. The format of a value in an

FPR is one of the valid numeric formats: single or double floating point, and word or long fixed

point. Otherwise the value is either uninterpreted or unknown.

The value in an FPR is always set when a va register as follows:lue is written to the

• When a data transfer instruction writes binary data into an FPR (a load destination of LWC1,

LDC1 MTC1, or instructions), the FPR receives a binary value that is uninterpreted.

• A computational or FP register move instruction that produces a result of type fmt puts a

value of type fmt into the result register.

When an FPR with an uninterpreted value is used as a source operand by an instruction that

requires a value of format fmt, the binary contents are interpreted as an encoded value in format

fmt fmt, and the value in the FPR changes to a value of format . The binary contents cannot be

reinterpreted in a different format.

If an FPR contains a value of format fmt, a computational instruction must not use the FPR as a

source operand of a different format. If this case occurs, the value in the register becomes

unknown, and the result of the instruction is also a value that is unknown. Using an FPR

containing an unknown value as a source operand produces a result that has an unknown value.

The format of the value in the FPR is unchanged when it is read by a data transfer instruction (a

store i.e. source operand of SWC1 SDC1, , or MFC1 instructions). A data transfer instruction

produces a binary encoding of the value contained in the FPR. If the value in the FPR is

unknown, the encoded binary value produced by the operation is not defined.

FPR[32:63] - Undefined/Unused FPR[0:31] - Data Word

FPR[0:63] - Data Double Word/Long Word

PIC32 Family Reference Manual

50.12.3.3 32-BIT AND 64-BIT BINARY DATA TRANSFER

The data transfer instructions move words and double words between the FPU FPRs and the

system.

The operations of the word and double word load and move-to instructions are shown in

Figure 50-20 and Figure 50-21, respectively.

The store and move-from instructions do the reverse, reading data from the location that the

corresponding load or move-to instruction had written.

Figure 50-20: FPU Word Load and Move-to Operations

Figure 50-21: FPU Double Word Load and Move-to Operations

FR bit = 1FR bit = 0

63 0 63 0

Reg 0 Initial Value 1 Reg 0 Initial Value 1

Reg 1 Initial Value 2 Reg 2 Initial Value 2

LWC1 f0, 0(r0) / MTC1 f0, r0

63 0 63 0

Reg 0 Undefined/Unused Data Word (0) Reg 0 Undefined/Unused Data Word (0)

Reg 1 Initial Value 2 Reg 2 Initial Value 2

LWC1 f1, 4(r0) / MTC1 f1, r4

63 0 63 0

Reg 0 Undefined/Unused Data Word (0) Reg 0 Data Word (4) Data Word (0)

Reg 1 Undefined/Unused Data Word (4) Reg 2 Initial Value 2

FR bit = 1FR bit = 0

63 0 63 0

Reg 0 Initial Value 1 Reg 0 Initial Value 1

Reg 1 Initial Value 2 Reg 2 Initial Value 2

LDC1 f0, 0(r0)

63 0 63 0

Reg 0 Data Double Word (0) Reg 0 Data Double Word (0)

Reg 1 Initial Value 2 Reg 2 Initial Value 2

LDC1 f1, 8(r0)

63 0

Reg 0 Data Double Word (0) (Illegal when FR bit = 0)

Reg 1 Data Double Word (9)

Section 50. CPU for Devices with MIPS32® microAp-

50.12.4 Floating Point Instruction Overview

The FPU instructions are divided into these categories:

•FPU Data Transfer Instructions

•FPU Arithmetic Instructions

•FPU Conversion Instructions

•FPU Formatted Operand-Value Move Instructions

•FPU Conditional Branch Instructions

•FPU Miscellaneous Instructions

The instructions are described in detail in Chapter 14, “M5150 Processor Core Instructions”

of the “MIPS32® M5150 Processor Core Family Software User’s Manual”. This document is

available for download by registered users from the Imagination Technologies Ltd. website

(www.imgtec.com).

50.12.4.1 FPU DATA TRANSFER INSTRUCTIONS

The FPU has two register sets: Coprocessor General Registers (FPRs) and Coprocessor Control

Registers (FCRs). The FPU has a load/store architecture: all computations are done on data held

in coprocessor general registers.

The control registers are used to control FPU operation. Data is transferred between registers

and the rest of the system with dedicated load, store, and move instructions. The transferred data

is treated as unformatted binary data. No format conversions are performed, and therefore no

IEEE floating point exceptions can occur.

Table 50-11: FPU Data Transfer Instructions

All coprocessor loads and stores operate on naturally aligned data items. An attempt to load or

store to an address that is not naturally aligned for the data item causes an Address Error

exception. The address of a word or double word is the smallest byte address in the object. For

the PIC32 architecture this is the least-significant byte.

50.12.4.2 FPU DATA TRANSFER INSTRUCTIONS ADDRESSING

The FPU has loads and stores using the same register + offset addressing as that used by the

CPU. Moreover, for the FPU only, there are load a ing register + registernd store instructions us

addressing.

Table Table 50-12 and Table 50-13 list the FPU data transfer instructions.

Table 50-12: FPU Load and Store Instructions

Transfer Direction Transferred Data

FPU general register <-> Memory Word/double word load/store

FPU general register <-> CPU general register Word move

FPU control register <-> CPU general register Word move

Mnemonic Instruction Addressing Mode

LDC1 Load Double word to Floating Point Register + offset

LWC1 Load Word to Floating Point Register + offset

SDC1 Store Double word from Floating Point Register + offset

SWC1 Store Word from Floating Point Register + offset

LDXC1 Load Double word Indexed to Floating Point Register + Register

LUXC1 Load Double word Indexed Unaligned to Floating Point Register + Register

LWXC1 Load Word Indexed to Floating Point Register + Register

SDXC1 Store Double word Indexed from Floating Point Register + Register

SUXC1 Store Double word Indexed Unaligned from Floating Point Register + Register

SWXC1 Store Word Indexed from Floating Point Register + Register

PIC32 Family Reference Manual

50.12.4.5 FPU FORMATTED OPERAND-VALUE MOVE INSTRUCTIONS

These instructions move formatted operand values among FPU general registers. A particular

operand type must be moved by the instruction that handles that type. There are three kinds of

move instructions:

• Unconditional move

• Conditional move that tests an FPU true/false condition code

• Conditional move that tests a CPU general-purpose register against zero

Conditional move instructions operate in a way that might be unexpected. They always force the

value in the destination register to become a value of the format specified in the instruction. If the

destination register does not contain an operand of the specified format before the conditional

move is executed, the contents become undefined. For more information, see the individual

descriptions of the conditional move instructions in “MIPS32

® Architecture Reference Manual,

Volume II” and “microMIPS32™ Architecture Reference Manual, Volume II”. These documents

are available for download by registered users from the Imagination Technologies Ltd. website

(www.imgtec.com).

Table Table 50-18 lists the formatted operand-value move instructions.

Table 50-18: FPU Formatted Operand Move Instructions

50.12.4.6 FPU CONDITIONAL BRANCH INSTRUCTIONS

The FPU has PC-relative conditional branch instructions that test condition codes set by FPU

compare instructions (C.cond.fmt).

All branches have an architectural delay of one instruction. When a branch is taken, the

instruction immediately following the branch instruction is said to be in the branch delay slot. It is

executed before the branch to the target instruction takes place.

Conditional branches come in two versions, depending upon how they handle an instruction in

the delay slot when the branch is not taken and execution falls through:

• Branch instructions execute the instruction in the delay slot.

• Branch likely instructions do not execute the instruction in the delay slot if the branch is not

taken (they are said to nullify the instruction in the delay slot).

The MIPS architecture defines eight condition codes for use in compare and branch instructions.

For backward compatibility with previous revisions of the ISA, condition code bit 0 and condition

code bits 1 through 7 are in discontinuous fields in the FCSR.

Table 50-19 lists the conditional branch (branch and branch likely) FPU instructions.

Table 50-19: FPU Conditional Branch Instructions

Mnemonic Instruction

MOV.fmt Floating Point Move

MOVF.fmt Floating Point Move Conditional on FP False

MOVT.fmt Floating Point Move Conditional on FP True

MOVN.fmt Floating Point Move Conditional on Nonzero

MOVZ.fmt Floating Point Move Conditional on Zero

Note: Although the Branch Likely instructions are included, software is strongly encour-

aged to avoid the use of the Branch Likely instructions, as they will be removed from

a future revision of the MIPS architecture.

Mnemonic Instruction

BC1F Branch on FP False

BC1T Branch on FP True

BC1FL Branch on FP False Likely. See Note 1.

BC1FT Branch on FP True Likely. See Note 1.

Note 1: Deprecated FPU instruction. Software should avoid their use.

Section 50. CPU for Devices with MIPS32® microAp-

50.12.4.7 FPU MISCELLANEOUS INSTRUCTIONS

The MIPS32 architecture defines various miscellaneous instructions that conditionally move one

CPU general register to another, based on an FPU condition code.

Table 50-20: CPU Conditional Move on FPU True/False Instructions

50.12.5 Floating Point Exceptions Overview

There are five exception conditions defined by the IEEE 754 Standard:

• Invalid Operation Exception

• Division By Zero Exception

• Underflow Exception

• Overflow Exception

• Inexact Exception

There is also a MIPS-specific exception condition, the Unimplemented Operation Exception, that

is used to signal a need for software emulation of an instruction.

Normally an IEEE arithmetic operation can cause only one exception condition. The only case in

which two exceptions can occur simultaneously are Inexact With Overflow and Inexact With

Underflow.

At the program’s control an IEEE exception condition can either cause a trap or not cause a trap.

The IEEE 754 Standard specifies the result to be delivered if no trap is taken. The FPU will supply

these results whenever the exception condition does not result in a trap. The default action taken

depends on the type of exception condition, and in the case of the Overflow and Underflow, the

current rounding mode.

Table 50-21 summarizes the default results supplied by the FPU.

FPU exceptions are implemented in the PIC32 FPU architecture with the Cause, Enables, and

Flags fields of the FCSR. The flag bits implement IEEE exception status flags and the cause and

enable bits control exception trapping.

Each field has a bit for each of the five IEEE exception conditions. The Cause field has an

additional exception bit, Unimplemented Operation, that could be used to trap for software

emulation assistance. If an exception type is enabled through the Enables field of the FCSR, the

FPU is operating in precise exception mode for this type of exception.

50.12.5.1 FLOATING POINT PRECISE EXCEPTION MODE

In precise exception mode, a trap occurs before the instruction that causes the trap or any

following instruction can complete and write its results. So the software trap handler can resume

execution of the interrupted instruction stream after handling the exception, if desired.

The Cause field reports per-bit instruction exception conditions. The cause bits are written during

each floating point arithmetic operation to show any exception conditions that arise during the

operation. A cause bit is set to ‘1’ if its corresponding exception condition arises; otherwise, it is

cleared to ‘0’.

A floating point trap is generated any time both a cause bit and its corresponding enable bit are

set. This case occurs either during the execution of a floating point operation or when moving a

value into the FCSR. There is no enable bit for Unimplemented Operations: this exception always

generates a trap.

In a trap handler, exception conditions that arise during any trapped floating point operations are

reported in the Cause field. Before returning from a floating point interrupt or exception, or before

setting cause bits with a move to the FCSR, software first must clear the enabled cause bits by

executing a move to the FCSR to prevent the trap from being erroneously retaken.

Mnemonic Instruction

MOVN Move Conditional on FP False

MOVZ Move Conditional on FP True

Section 50. CPU for Devices with MIPS32® microAp-

50.12.5.3 FLOATING POINT DIVISION BY ZERO EXCEPTION

The divide operation signals a Division By Zero exception if the divisor is zero and the dividend

is a finite nonzero number. When no precise trap occurs, the result is a correctly signed infinity.

Divisions (0/0 and ∞/0) do not cause the Division By Zero exception. The result of (0/0) is an

Invalid Operation exception. The result of (

∞/0) is a correctly signed infinity.

50.12.5.4 FLOATING POINT UNDERFLOW EXCEPTION

There are two related events that contribute to underflow:

• Tininess: The creation of a tiny, nonzero result between ±2

E_min which, because it is tiny,

might cause some other exception later such as overflow on division. The IEEE 754

Standard allows choices in detecting tininess events. The PIC32/MIPS architecture specifies

that tininess be detected after rounding, when a nonzero result computed as though the

exponent range were unbounded would lie strictly between ±2

E_min.

• Loss of accuracy: The extraordinary loss of accuracy occurs during the approximation of

such tiny numbers by denormalized numbers. The IEEE 754 Standard allows choices in

detecting loss of accuracy events. The PIC32/MIPS architecture specifies that loss of

accuracy be detected as inexact result, when the delivered result differs from what would

have been computed if both the exponent range and precision were unbounded.

The way that an underflow is signaled depends on whether or not underflow traps are enabled:

• When an underflow trap is not enabled, underflow is signaled only when both tininess and

loss of accuracy have been detected. The delivered result might be zero, denormalized, or

±2E_min.

• When an underflow trap is enabled (through the FCSR Enables field), underflow is signaled

when tininess is detected regardless of loss of accuracy.

50.12.5.5 FLOATING POINT OVERFLOW EXCEPTION

An Overflow exception is signaled when the magnitude of a rounded floating point result (if the

exponent range is unbounded) is larger than the destination format’s largest finite number.

When no precise trap occurs, the result is determined by the rounding mode and the sign of the

intermediate result.

50.12.5.6 FLOATING POINT INEXACT EXCEPTION

An Inexact exception is signaled when one of the following occurs:

• The rounded result of an operation is not exact.

• The rounded result of an operation overflows without an overflow trap.

• When a denormal operand is flushed to zero.

50.12.5.7 FLOATING POINT UNIMPLEMENTED OPERATION EXCEPTION

The Unimplemented Operation exception is a MIPS-defined exception that provides software

emulation support. This exception is not IEEE-compliant.

The PIC32/MIPS architecture is designed so that a combination of hardware and software can

implement the FPU functionality. Operations not fully supported in hardware cause an

Unimplemented Operation exception, allowing software to perform the operation.

There is no enable bit for this condition. It will always causes a trap (but the condition is effectively

masked for all operations when FS = 1). After the appropriate emulation or other operation is

done in a software exception handler, the original instruction stream can be continued.

An Unimplemented Operation exception is taken when denormalized operands or tiny results are

encountered for instructions not supporting denormalized numbers and where such are not

handed by the FS/FO/FN bits.

Section 50. CPU for Devices with MIPS32® microAp-

Stage 3: FPU Pipeline: M2 Stage – Multiply Complete

The M2 stage has the following functionality:

• Multiplication is complete when the carry-save encoded product is compressed into binary

• Rounding is performed

• Exponent difference for addition path is calculated

Stage 4: FPU Pipeline: A1 Stage – Addition First Step

This stage performs the first step of the addition.

Stage 5: FPU Pipeline: A2 Stage - Addition Second and Final Step

This stage performs the second and final step of the addition.

Stage 6: FPU Pipeline: FP Stage – Result Pack

The FP stage has the following functionality:

• The result coming from the data path is packed into the IEEE 754 Standard format for the

FPR register file

• Overflow and underflow exceptional conditions are resolved

Stage 7: FPU Pipeline: FW Stage – Register Write

The result is written to the FPR register file.

50.12.6.2 FPU BYPASSING

The FPU pipeline implements extensive bypassing so that the results do not need to be written

into the register file and read back before they can be used, but can be forwarded directly to an

instruction already in the pipe.

Some bypassing is disabled when operating in 32-bit register file mode (the FR bit in the CP0

Status[26] register is ‘0’), due to the paired even-odd 32-bit registers that provide 64-bit registers.

Figure 50-23: PIC32 FPU Pipeline Bypass Paths

FR M1 M2 A1 A2 FP FW

A2 Bypass

FP Bypass

FW Bypass

PIC32 Family Reference Manual

50.12.6.3 FPU REPEAT RATE AND LATENCY

Table 50-22 shows the repeat rate and latency for the FPU instructions.

Note that cycles related to floating point operations are listed in terms of FPU clocks.

Table 50-22: FPU Latency and Repeat Rate

Op code

(see Note 1)

Latency

(FPU

Cycles)

Repeat Rate

(FPU Cycles)

ABS.[S,D], NEG.[S,D], ADD.[S,D], SUB.[S,D],

MUL.S,

MADD.S, MSUB.S, NMADD.S, MSUB.S

4 1

MUL.D, MADD.D, MSUB.D, NMADD.D, NMSUB.D 5 2

RECIP.S 13 10

RECIP.D 25 21

RSQRT.S 17 14

RSQRT.D 35 31

DIV.S SQRT.S, 17 14

DIV.D SQRT.D, 32 29

C.cond.[S,D] MOVF.fmt MOVT.fmt to and instruction/

MOVT MOVN BC1, , instruction

One-half 1

CVT.D.S CVT.[S,D].[W,L], 4 1

CVT.S.D 6 1

CVT.[W,L].[S,D],

CEIL.[W,L].[S,D], FLOOR.[W,L].[S,D],

ROUND.[W,L].[S,D],

TRUNC.[W,L].[S,D]

5 1

MOV.[S,D], MOVF.[S,D], MOVN.[S,D], MOVT.[S,D],

MOVZ.[S,D]

4 1

LWC1, LDC1, LDXC1, LUXC1, LWXC1 3 1

MTC1, MFC1 2 1

Legend: S = Single; D = Double; W = Word; L = Long Word

Section 50. CPU for Devices with MIPS32® microAp-

50.12.6.4 FLOATING POINT 2008 FPU SUPPORT

The PIC32 FPU implements the following status/control bits to provide greater compatibility with

the IEEE 754 Standard Floating Point released in 2008:

• The Has2008 bit (FIR[23]) will always read as ‘1’ to signify that 2008 FPU is implemented.

• The MAC2008 bit (FCSR[20]) will always read as ‘0’ to signify that Fused Multiply Add

operation is not implemented.

• The ABS2008 bit (FCSR[19]) is always set to ‘1’ which makes ABS and NEG instructions

non-arithmetic instructions. All floating point exceptions will be disabled.

• The NAN2008 bit (FCSR[18]) is always set to ‘1’ to show Quiet and signaling NaN

encodings recommended by the IEEE 754-2008 Standard. In addition, the following

behaviors are implemented:

- In the case of one or more QNaN operands (no SNaN), the QNaN operand is propagated

from one of the input register operands (in order of priority): fs, ft, and fr (see the following

Note).

- When SNaN is used as an input, and exceptions are disabled, QNaN is the expected

output

- The QNaN output will not be a fixed value. To comply with IEEE, an input NaN should

produce a NaN with the payload of the input NaN if representable in the destination

format, where the payload is defined as the Mantissa field less its most-significant bit.

- If ABS2008 = 1 and MAC2008 = 0 (as it always is in PIC32), the sign of NMADD and

NMSUB do not flip the sign of any QNaN input, and the sign is retained and propagated

to the output.

- When a NaN is an input, the output will be one of the input NaNs with as much of the

mantissa preserved as possible.

- SNaN inputs have higher priority than QNaN inputs and then fs has higher priority than ft

which has higher priority than fr register (see the following Note).

- The sign of the selected NaN input is preserved. If the input that is selected for the output

is already a QNaN, the entire mantissa is preserved. However, if the input that is selected

for the output is a SNaN, the most significant bit of the SNaN mantissa is complemented

to convert the SNaN into a QNaN. If this conversion to a QNaN would result in an infinity,

the next most significant bit of the mantissa is set.

- For CVT.s.d CVT.d.s, the NaN mantissa most significant bits are preserved. For , the

NaN mantissa is padded with ‘0’s in the least significant bits.

- For multiply-add, if both fs/ft and fr registers are QNaNs, the multiply produces a QNaN

based upon fs/ft, and this QNaN has priority over fr in the add operation. However, if both

fs ft fr/ and registers are SNaNs and the invalid trap is not enabled, the multiply generates

a QNaN based upon fs/ft, which is then added to the signaling fr register and the signaling

fr has priority

- When a NaN is needed for output but there is no NaN input, a positive QNaN is created

that has all other mantissa bits set.

50.12.6.5 IEEE 754-1985 STANDARD

The IEEE 754-1985 Standard, “IEEE Standard for Binary Floating-Point Arithmetic” defines the

following:

• Floating Point data types

• The basic arithmetic, comparison, and conversion operations

• A computational model

The IEEE 754-1985 St fine specific processing resandard does not de ources nor does it define

an instruction set. For additional information about the IEEE 754-1985 standard, visit the IEEE

Web page at http://stdsbbs.ieee.org/.

Note: Registers fs ft, , and fr are floating point registers that occur in the multiply-add

floating point operations. For example: MADD.D fd, fr, fs, ft.

PIC32 Family Reference Manual

50.13 COPROCESSOR 0 (CP0) REGISTERS

The PIC32 uses a special register interface to communicate status and control information

between system software and the CPU. This interface is called Coprocessor 0, or CP0. The

features of the CPU that are visible through Coprocessor 0 are:

• Translation Lookaside Buffer (TLB)

• Core timer

• Interrupt and exception control

• Virtual memory configuration

• Shadow register set control

• Processor identification

• Debugger control

• Performance counters

System software accesses the registers in CP0 using coprocessor instructions such as MFC0

and MTC0. Table 50-23 describes the CP0 registers found on PIC32 devices.

Table 50-23: CP0 Registers

Number Register Name Function

0 Index Index into the TLB array (MPU only).

1 Random Randomly generated index into the TLB array (MPU only).

2 EntryLo0 Low-order portion of the TLB entry for even-numbered virtual pages (MPU only).

3 EntryLo1 Low-order portion of the TLB entry for odd-numbered virtual pages (MPU only).

4 Context/

UserLocal

Pointer to the page table entry in memory (MPU only).

User information that can be written by privileged software and read via the RDHWR

instruction.

5 PageMask/

PageGrain

PageMask controls the variable page sizes in TLB entries. PageGrain enables support

of 1 KB pages in the TLB (MPU only).

6 Wired Controls the number of fixed (i.e., wired) TLB entries (MPU only).

7 HWREna Enables access via the RDHWR instruction to selected hardware registers in

Non-privileged mode.

8 BadVAddr Reports the address for the most recent address-related exception.

BadInstr Reports the instruction that caused the most recent exception.

BadInstrP Reports the branch instruction if a delay slot caused the most recent exception.

9 Count Processor cycle count.

10 EntryHi High-order portion of the TLB entry (MPU only).

11 Compare Core timer interrupt control.

12 Status Processor status and control.

IntCtl Interrupt control of vector spacing.

SRSCtl Shadow register set control.

SRSMap Shadow register mapping control.

View_IPL Allows the Priority Level to be read/written without

extracting or inserting that bit from/to the Status register.

SRSMAP2 Contains two 4-bit fields that provide the mapping from a vector number to the shadow

set number to use when servicing such an interrupt.

GuestCtl0 Control of Virtualized Guest OS"

GTOffset Guest Timer Offset

13 Cause Describes the cause of the last exception.

NestedExc Contains the error and exception level status bit values that existed prior to the current

exception.

View_RIPL Enables read access to the RIPL bit that is available in the Cause register.

Section 50. CPU for Devices with MIPS32® microAp-

Note: Refer to the “CPU” chapter in the specific device data sheet to determine the avail-

ability of specific CPU Registers.

14 EPC Program counter at last exception.

NestedEPC Contains the exception program counter that existed prior to the current exception.

15 PRID Processor identification and revision

Ebase Exception base address of exception vectors.

CDMMBase Common device memory map base.

16 Config Configuration register.

Config1 Configuration register 1.

Config2 Configuration register 2.

Config3 Configuration register 3.

Config4 Configuration register 4.

Config5 Configuration register 5.

Config7 Configuration register 7.

17 LLAddr Load link address (MPU only).

18 WatchLo Low-order watchpoint address (MPU only).

19 WatchHi High-order watchpoint address (MPU only).

20-22 Reserved Reserved in the PIC32 core.

23 Debug EJTAG debug register.

TraceControl EJTAG trace control.

TraceControl2 EJTAG trace control 2.

UserTraceData1 EJTAG user trace data 1 register.

TraceBPC EJTAG trace breakpoint register.

Debug2 Debug control/exception status 1.

24 DEPC Program counter at last debug exception.

UserTraceData2 EJTAG user trace data 2 register.

25 PerfCtl0 Performance counter 0 control.

PerfCnt0 Performance counter 0.

PerfCtl1 Performance counter 1 control.

PerfCnt1 Performance counter 1.

26 ErrCtl Software test enable of way-select and data RAM arrays for I-Cache and D-Cache

(MPU only).

27 CacheErr Records information about Cache/SPRAM parity errors.

28 TagLo/DataLo Low-order portion of cache tag interface (MPU only).

29 Reserved Reserved in the PIC32 core.

30 ErrorEPC Program counter at last error.

31 DeSAVE Debug handler scratchpad register.

KScratch1 Scratch register for Kernel mode.

KScratch2 Scratch register for Kernel mode.

Table 50-23: CP0 Registers (Continued)

Number Register Name Function

PIC32 Family Reference Manual

50.13.1 Index Register (CP0 Register 0, Select 0)

(MPU only)

The Index register is a 32-bit read/write register that contains the index used to access the TLB

for TLBP, TLBR, and TLBWI instructions.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x U-0 U-0 U-0 U-0 U-0 U-0 U-0

P — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — Index[4:0](1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 P: Probe Failure Detect bit

1 = The previous TLBP instruction failed to find a match in the TLB

0 = The previous TLBP instruction found a match in the TLB

bit 30-5 Unimplemented: Read as ‘0’

bit 4-0 Index[4:0]: Index to TLB Entry Affected by the TLBR and TLBW Instructions bits

(1)

11111 = TLB Entry 31

•

00000 = TLB Entry 0

Note 1: Depending on the configuration of used. The number of TLB entries the MMU, not all bits may be

supported by the MMU can be read from the MMU Size[5:0] field of the Config1 CP0 register.

PIC32 Family Reference Manual

50.13.3 EntryLo0 Register (CP0 Register 2, Select 0) and

EntryLo1 Register (CP0 Register 3, Select 0)

(MPU only)

The pair of EntryLo registers act as the interface between the TLB and the TLBR TLBWI, , and

TLBWR instructions. EntryLo0 holds the entries for even pages and EntryLo1 holds the entries for

odd pages.

The contents of the EntryLo0 and EntryLo1 registers are undefined after an address error, TLB

invalid, TLB modified, or TLB refill exception.

EntryLo1; Odd Page TLB Entries Register; CP0 Register 3, Select 0

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-x R/W-x

RI XI — — — — PFN[19:18]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PFN[17:10]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PFN[9:2]

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PFN[1:0] C[2:0] D V G

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 RI: Read Inhibit bit

If this bit is set, an attempt to read data from the page causes a TLB Invalid exception, even if the V

(Valid) bit is set. The RI bit is enabled only if the RIE bit of the PageGrain register is set. If the RIE bit of

PageGrain is not set, the RI bit of EntryLo0/EntryLo1 is a reserved ‘0’ bit as per the MIPS32 specification.

bit 30 XI: Execute Inhibit bit

If this bit is set, an attempt to fetch from the page causes a TLB Invalid exception, even if the V (Valid) bit is

set. The XI bit is enabled only if the XIE bit of the PageGrain register is set. If the XIE bit of PageGrain is not

set, the XI bit of EntryLo0/EntryLo1 is a reserved ‘0’ bit as per the MIPS32 specification.

bit 29-26 Unimplemented: Read as ‘0’

bit 25-6 PFN[19:0]: Page Frame Number bits

Contributes to the definition of the high-order bits of the physical address.

The PFN[19:0] bits correspond to bits [31:12] of the physical address.

bit 5-3 C[2:0]: Coherency Page Attribute bits

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = Cacheable, non-coherent, write-back, write allocate

010 = Uncached

001 = Cacheable, non-coherent, write-through, write allocate

000 = Cacheable, non-coherent, write-through, no write allocate

bit 2 D: Dirty (write-enable) bit

1 = Stores to the page are permitted

0 = Stores to the page cause a TLB modified exception

bit 1 V: Valid bit

1 = Accesses to the page are permitted

0 = Accesses to the page cause a TLB invalid exception

bit 0 G: Global bit

On a TLB write, the logical AND of the G bits in both the EntryLo0 and EntryLo1 register becomes the G bit

in the TLB entry. If the TLB entry G bit is a ‘1’, the ASID comparisons are ignored during TLB matches. On

a read from a TLB entry, the G bits of both EntryLo0 and EntryLo1 reflect the state of the TLB G bit.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.6 PageMask Register (CP0 Register 5, Select 0)

(MPU only)

The PageMask register is a read/write register used for reading from and writing to the TLB. It

holds a comparison mask that sets the variable page size for each TLB entry, as shown in

Table 50-24.

Table 50-24: Values for the Mask bits of the PageMask Register

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — Mask[15:11]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Mask[10:3]

15:8 R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0

Mask[2:0] — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-13 Mask[15:0]: Virtual Address Mask bits

When this bit is a ‘1’, this indicates that the corresponding bit of the virtual address should not participate in

the TLB match.

bit 12-0 Unimplemented: Read as ‘0’

Page

Size

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13

4 KB 0000000000000000

16 KB 0000000000000011

64 KB 0000000000001111

256 KB 0000000000111111

1 MB 0000000011111111

4 MB 0000001111111111

16 MB 0000111111111111

64 MB 0011111111111111

256 MB 1111111111111111

PIC32 Family Reference Manual

50.13.7 PageGrain Register (CP0 Register 5, Select 1)

(MPU only)

The PageGrain register is used on the PIC32 device to enable or disable the read and execute

inhibit bits in the EntryLo0 and EntryLo1 registers.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0

RIE XIE — — IEC — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 RIE: Read Inhibit Enable bit

1 = RI bit of EntryLo0 and EntryLo1 registers is enabled

0 = RI bit of EntryLo0 and EntryLo1 registers is disabled and is not writable

bit 30 XIE: Execute Inhibit Enable bit

1 = XI bit of EntryLo0 and EntryLo1 registers is enabled

0 = XI bit of EntryLo0 and EntryLo1 registers is disabled and is not writable

bit 29-28 Unimplemented: Must be written as ‘0’; returns ‘0’ on a read

bit 27 IEC: Enable Read-Inhibit and Execute-Inhibit Exception Codes bit

1 = Read-Inhibit exceptions use the TLBRI exception code. Execute-Inhibit exceptions use the

TLBXI exception code

0 = Read-Inhibit and Execute-Inhibit exceptions both use the TLBL exception code

bit 26-0 Unimplemented: Must be written as ‘0’; returns ‘0’ on a read

Section 50. CPU for Devices with MIPS32® microAp-

50.13.8 Wired Register (CP0 Register 6, Select 0)

(MPU Only)

The Wired register is a read/write register that specifies the boundary between the wired and

random entries in the TLB. The width of the Wired field is calculated in the same manner as that

described for the Index register. Wired entries are fixed, non-replaceable entries that are not

overwritten by a TLBWR instruction. Wired entries can be overwritten by a TLBWI instruction.

The Wired register is reset to zero by a Reset exception. Writing the Wired register causes the

Random register to reset to its upper bound.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — Wired[4:0](1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-5 Unimplemented: Read as ‘0’

bit 4-0 Wired[4:0]: TLB Wired Boundary bits(1)

11111 = Entry 31 is random, entries 0-30 are wired

•

01111 = Entry 15 is random, entries 0-14 are wired

•

00111 = Entries 7 and above are random, below 7 are wired

•

00000 = All 16 entries are random

Note 1: Depending on the configuration of the MMU, not all bits may be used. The number of TLB entries

supported by the MMU can be read from the MMU Size[5:0] field of the Config1 CP0 register.

PIC32 Family Reference Manual

50.13.9 HWREna Register (CP0 Register 7, Select 0)

The HWREna register contains a bit mask that determines which hardware registers are

accessible through the RDHWR instruction.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— — ULR — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — MASK[3:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29 ULR: User Local Register bit

1 = Enable unprivileged access to UserLocal register

0 = Disable unprivileged access to UserLocal register

This bit provides read access to the Coprocessor 0 UserLocal register.

bit 28-4 Unimplemented: Read as ‘0’

bit 3-0 MASK[3:0]: Bit Mask bits

1 = Access is enabled to corresponding hardware register

0 = Access is disabled

Each of these bits enables access by the RDHWR instruction to a particular hardware register (which may

not be an actual register). See the RDHWR instruction for a list of valid hardware registers.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.10 BadVAddr Register (CP0 Register 8, Select 0)

BadVAddr is a read-only register that captures the most recent virtual address that caused an

address error exception. Address errors are caused by executing load, store, or fetch operations

from unaligned addresses, or by trying to access Kernel mode addresses from User mode.

For devices with the MPU core, the BadVAddr register will also capture the most recent virtual

address that caused a TLB refill, TLB invalid, or TLB modified exception.

BadVAddr does not capture address information for bus errors, because they are not addressing

errors.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr[31:24]

23:16 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr[23:16]

15:8

R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr[15:8]

7:0

R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BadVAddr[31:0]: Bad Virtual Address bits

Captures the virtual address that caused the most recent address error exception.

PIC32 Family Reference Manual

50.13.11 BadInstr Register (CP0 Register 8, Select 1)

(M-Class only)

The BadInstr register is an optional read-only register that captures the most recent instruction

that caused one of the following exceptions:

• Instruction Validity: Coprocessor Unusable, Reserved Instruction

• Execution Exception: Integer Overflow, Trap, System Call, Breakpoint, Floating-point,

Coprocessor 2 exception

• Addressing: Address Error, TLB Refill, TLB Invalid, TLB Read Inhibit, TLB Execute Inhibit,

TLB Modified

The BadInstr register is provided to allow acceleration of instruction emulation. The BadInstr reg-

ister is only set by exceptions that are synchronous to an instruction. The BadInstr register is not

set by Interrupts or by NMI, Machine check, Bus Error, Cache Error, Watch, or EJTAG excep-

tions.

When a synchronous exception occurs for which there is no valid instruction word (for example

TLB Refill - Instruction Fetch), the value stored in BadInstr is unpredictable.

Presence of the BadInstr register is indicated by the Config3BI bit. The BadInstr register is instan-

tiated per-VPE in an MT ASE processor.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstr[31:24]

23:16 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstr[23:16]

15:8 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstr[15:8]

7:0 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstr[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BadInstr[31:0]: Bad (Faulting) Instruction Word bits

Instruction words smaller than 32 bits are placed in bits 15:0, with bits 31:16 containing ‘0’.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.12 BadInstrP Register (CP0 Register 8, Select 2)

(M-Class only)

The BadInstrP register is an optional register that is used in conjunction with the BadInstr

is in a branch delay slot.

The BadInstrP register is updated for these exceptions:

• Instruction Validity: Coprocessor Unusable, Reserved Instruction

• Execution Exception: Integer Overflow, Trap, System Call, Breakpoint, Floating-point,

Coprocessor 2 exception

• Addressing: Address Error, TLB Refill, TLB Invalid, TLB Read Inhibit, TLB Execute Inhibit,

TLB Modified

The BadInstrP register is provided to allow acceleration of instruction emulation. The BadInstrP

is not set by Interrupts or by NMI, Machine check, Bus Error, Cache Error, Watch, or EJTAG

exceptions. When a synchronous exception occurs, and the faulting instruction is not in a branch

delay slot, then the value stored in BadInstrP is unpredictable.

Presence of the BadInstrP register is indicated by the Config3BP bit. The BadInstrP register is

instantiated per-VPE in an MT ASE processor.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstrP[31:24]

23:16 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstrP[23:16]

15:8 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstrP[15:8]

7:0 R-x R-x R-x R-x R-x R-x R-x R-x

BadInstrP[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BadInstrP[31:0]: Bad Prior Branch Instruction bits

Instruction words smaller than 32 bits are placed in bits 15:0, with bits 31:16 containing ‘0’.

PIC32 Family Reference Manual

50.13.13 Count Register (CP0 Register 9, Select 0)

The Count register acts as a timer, incrementing at a constant rate, whether or not an instruction

is executed, retired, or any forward progress is made through the pipeline. The counter

increments every other clock, if the DC bit in the Cause register is ‘0’.

Count can be written for functional or diagnostic purposes, including at Reset or to synchronize

processors.

By writing the COUNTDM bit in the Debug register, it is possible to control whether Count

continues to increment while the processor is in Debug mode.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT[31:24]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT[23:16]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT[15:8]

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 COUNT[31:0]: Interval Counter bits

This value is incremented every other clock cycle.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.14 EntryHi Register (CP0 Register 10, Select 0)

(MPU only)

The EntryHi register contains the virtual address match information used for TLB read, write, and

access operations.

A TLB exception (TLB Refill, TLB Invalid, or TLB Modified) causes bits VA31...13 of the virtual

address to be written into the VPN2 field of the EntryHi register. A TLBR instruction writes the

EntryHi register with the corresponding fields from the selected TLB entry. The ASID field is

written by software with the current address space identifier value and is used during the TLB

comparison process to determine TLB match.

Because the ASID field is overwritten by a TLBR instruction, software must save and restore the

value of ASID around use of the TLBR. This is especially important in TLB Invalid and TLB

Modified exceptions, and in other memory management software.

The VPN2 field of the EntryHi r dress error exception, and mayegister is not defined after an ad

be modified by hardware during the address error exception sequence. Software writes of the

EntryHi register (via MTC0) do not cause the implicit write of address-related fields in the

BadVAddr or Context registers.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

VPN2[18:11]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

VPN2[10:3]

15:8 R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0

VPN2[2:0] — — — — —

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ASID[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 VPN2[18:11]: Virtual Page Number bits

These bits are written by hardware on a TLB exception or on a TLB read, and are written by software before

a TLB write.

bit 12-8 Unimplemented: Read as ‘0’

bit 7-0 ASID[7:0]: Address Space Identifier bits

These bits are written by hardware on a TLB read and by software to establish the current ASID value for a

TLB write and against which TLB references match each entry’s TLB ASID field.

PIC32 Family Reference Manual

50.13.15 Compare Register (CP0 Register 11, Select 0)

The Compare register acts in conjunction with the Count register to implement a timer and timer

interrupt function. Compare maintains a stable value and does not change on its own.

When the value of Count equals the value of Compare, the CPU asserts an interrupt signal to the

system interrupt controller. This signal will remain asserted until Compare is written.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE[31:24]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE[23:16]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE[15:8]

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 COMPARE[31:0]: Interval Count Compare Value bits

Section 50. CPU for Devices with MIPS32® microAp-

50.13.16 Status Register (CP0 Register 12, Select 0)

The read/write Status register contains the operating mode, interrupt enabling, and the diagnostic

states of the processor. The bits of this register combine to create operating modes for the processor.

50.13.16.1INTERRUPT ENABLE

Interrupts are enabled when all of the following conditions are true:

• IE = 1

• EXL = 0

• ERL = 0

• DM = 0

If these conditions are met, the settings of the IPL bits enable the interrupts.

50.13.16.2OPERATING MODES

If the DM bit in the Debug register is ‘1’, the processor is in Debug mode; otherwise, the

processor is in either Kernel mode or User mode. The CPU Status register bit settings shown in

Table 50-25 determine User or Kernel mode:

Table 50-25: CPU Status Register Bits That Determine Processor Mode

Mode Bit/Setting

User (requires all of the following bits and values) UM = 1EXL = 0ERL = 0

Kernel (requires one or more of the following bit values) UM = 0EXL = 1ERL = 1

Note: The Status register CU0 bit (Status[28]) controls Coprocessor 0 accessibility. If

Coprocessor 0 is unusable, an instruction that accesses it generates an exception.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R/W-0 R/W-x R/W-0 R/W-0 R/W-x R/W-0

— — CU1(2) CU0 RP FR(2) RE MX(3)

23:16 U-0 R/W-1 R/W-0, HS, CS R/W-1 R/W-0 R/W-x U-0 R/W-0

— BEV TS(1) SR NMI IPL[7] — IPL[6]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 U-0

IPL[5:0] — —

7:0 U-0 U-0 U-0 R/W-x U-0 R/W-x R/W-x R/W-x

— — — UM — ERL EXL IE

Legend: HS = Set by hardware CS = Cleared by software

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

Note 1: This bit is only available on devices with the MPU core. Refer to the “CPU” chapter in the specific device

data sheet for availability.

2: This bit is only available on devices with the M-Class core. Refer to the specific device data sheet for

availability.

3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet for

availability.

PIC32 Family Reference Manual

bit 29 CU1: Coprocessor 1 Usable bit(2)

This bit allows access to Coprocessor 1. This bit can only be written if the FPU is configured. This bit will

read as ‘0’ if the FPU is not present.

1 = Access is allowed

0 = Access is not allowed

bit 28 CU0: Coprocessor 0 Usable bit

This bit controls access to Coprocessor 0.

1 = Access is allowed

0 = Access is not allowed

Coprocessor 0 is always usable when the processor is running in Kernel mode, independent of the state of

the CU0 bit.

bit 27 RP: Reduced Power bit

1 = Enables Reduced Power mode

0 = Disables Reduced Power mode

bit 26 FR: Floating Point Register Mode(2)

1 = Floating-point registers can contain any data type

0 = Floating-point registers can contain any 32-bit data type. 64-bit data types are stored in even-odd pairs

of registers

Note: This bit must be ignored on write and read as ‘0’ for CPUs with no FPU.

bit 25 RE: Reverse-endian Memory Reference Enable bit

Used to enable reverse-endian memory references while the processor is running in User mode

1 = User mode uses reversed endianness

0 = User mode uses configured endianness

Debug, Kernel, or Supervisor mode references are not affected by the state of this bit.

bit 24 MX: MIPS DSP Resource Enable bit(3)

This bit must be set prior to executing any DSP ASE instruction. An attempt to execute a DSP ASE

instruction while this bit is cleared will result in a DSP State Disabled exception.

1 = Access is enabled

0 = Access is disabled

bit 23 Unimplemented: Read as ‘0’

bit 22 BEV: Bootstrap Exception Vector Control bit

Controls the location of exception vectors.

1 = Bootstrap

0 = Normal

bit 21 TS: TLB Shutdown Control bit(1)

Indicates that the TLB has detected a match on multiple entries. This bit is also set if a TLBWI or TLBWR

instruction is issued that would cause a TLB shutdown condition if allowed to complete. A machine check

exception is also issued.

1 = TLB shutdown event

0 = No TLB shutdown event

Software can only write a '0' to this bit to clear it and cannot force a '0' to '1' transition.

bit 20 SR: Soft Reset bit

Indicates that the entry through the Reset exception vector was due to a Soft Reset.

1 = Soft Reset; this bit is always set for any type of reset on the PIC32 core

0 = Not used on PIC32

Software can only write a ‘0’ to this bit to clear it and cannot force a ‘0’ to ‘1’ transition.

Note 1: This bit is only available on devices with the MPU core. Refer to the “CPU” chapter in the specific device

data sheet for availability.

2: This bit is only available on devices with the M-Class core. Refer to the specific device data sheet for

availability.

3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet for

availability.

Section 50. CPU for Devices with MIPS32® microAp-

bit 19 NMI: Non-Maskable Interrupt bit

Indicates that the entry through the reset exception vector was due to a NMI.

1 = NMI

0 = Not NMI (Soft Reset or Reset)

Software can only write a ‘0’ to this bit to clear it and cannot force a ‘0’ to ‘1’ transition.

bit 18 IPL[7]: Interrupt Priority Level bits

This field is the encoded (0-256) value of the current IPL. An interrupt will be signaled only if the requested

IPL is higher than this value.

bit 17 Unimplemented: Read as ‘0’

bit 16-10 IPL[6:0]: Interrupt Priority Level bits

This field is the encoded (0-256) value of the current IPL. An interrupt will be signaled only if the requested

IPL is higher than this value.

bit 9-5 Unimplemented: Read as ‘0’

bit 4 UM: User Mode bit

This bit denotes the base operating mode of the processor. On the encoding of this bit is:

1 = Base mode is User mode

0 = Base mode in Kernel mode

The processor can also be in Kernel mode if ERL or EXL is set, regardless of the state of the UM bit.

bit 3 Unimplemented: Read as ‘0’

bit 2 ERL: Error Level bit

Set by the processor when a Reset, Soft Reset, NMI or Cache Error exception are taken.

1 = Error level

0 = Normal level

When ERL is set:

• Processor is running in Kernel mode

• Interrupts are disabled

•ERET instruction will use the return address held in the ErrorEPC register instead of the EPC register

• Lower 229 bytes of kuseg are treated as an unmapped and uncached region. This allows main mem-

ory to be accessed in the presence of cache errors. The operation of the processor is undefined if the

ERL bit is set while the processor is executing instructions from kuseg.

bit 1 EXL: Exception Level bit

Set by the processor when any exception other than Reset, Soft Reset, or NMI exceptions is taken.

1 = Exception level

0 = Normal level

When EXL is set:

• Processor is running in Kernel mode

• Interrupts are disabled

EPC, BD, and SRSCtl will not be updated if another exception is taken.

bit 0 IE: Interrupt Enable bit

Acts as the master enable for software and hardware interrupts:

1 = Interrupts are enabled

0 = Interrupts are disabled

This bit may be modified separately via the DI and EI instructions

Note 1: This bit is only available on devices with the MPU core. Refer to the “CPU” chapter in the specific device

data sheet for availability.

2: This bit is only available on devices with the M-Class core. Refer to the specific device data sheet for

availability.

3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet for

availability.

PIC32 Family Reference Manual

50.13.17 IntCtl: Interrupt Control Register (CP0 Register 12, Select 1)

The IntCtl register controls the vector spacing of the PIC32 architecture.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

— PF ICE STKDEC[4:0]

15:8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

CLREXL APE USESTK — — — VS[4:3]

7:0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

VS[2:0] — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as ‘0’

bit 22 PF: Vector Prefetching Enable bit

1 = Vector Prefetching is Enabled

0 = Vector Prefetching is Disabled

bit 21 ICE: Interrupt Chaining Enable bit

1 = Interrupt chaining is Enabled

0 = Interrupt chaining is Disabled

bit 20-16 STKDEC[4:0]: Stack Pointer Decrement bits

For the Auto-Prologue feature, this is the number of 4-byte words that are decremented from the stack

pointer value.

31-4 = Specifies the number of words to be decremented

3-0 = Decrement 3 words (12 bytes)

bit 15 CLREXL: Clear KSU/ERL/EXL bit

For the Auto-Prologue feature and IRET instruction, this bit, if set, during Auto-Prologue and IRET interrupt

chaining, clears the KSU/ERL/EXL bits.

1 = Bits are cleared by these operations

0 = Bits are not cleared by these operations

bit 14 APE: Auto-Prologue Enable bit

1 = Auto-Prologue is enabled

0 = Auto-Prologue is disabled

bit 13 USEKSTK: Stack Use bit

Chooses which Stack to use during Interrupt Auto-Prologue.

1 = Use r29 of the Current SRS at the beginning of IAP

Used for environments where there are separate User mode and Kernel mode stacks. In this case, r29 of

the SRS used during IAP must be preinitialized by software to hold the Kernel mode stack pointer.

0 = Copy r29 of the Previous SRS to the Current SRS at the beginning of IAP

Used for Bare-Iron environments with only one stack.

bit 12-10 Unimplemented: Read as ‘0’

Section 50. CPU for Devices with MIPS32® microAp-

bit 9-5 VS[4:0]: Vector Spacing bits

These bits specify the spacing between each interrupt vector.

All other values are reserved. The operation of the processor is undefined if a reserved value is written to

these bits.

bit 4-0 Unimplemented: Read as ‘0’

Encoding Spacing Between Vectors (hex) Spacing Between Vectors (decimal)

0x00 0x000 0

0x01 0x020 32

0x02 0x040 64

0x04 0x080 128

0x08 0x100 256

0x10 0x200 512

PIC32 Family Reference Manual

50.13.18 SRSCtl Register (CP0 Register 12, Select 2)

The SRSCtl register controls the operation of GPR shadow sets in the processor.

Table 50-26: Sources for New CSS on an Exception or Interrupt

Exception Type Bit Source Condition Comment

Exception ESS All —

Non-Vectored Interrupt ESS IV bit = 0 (Cause[23]) Treat as exception

Vectored EIC Interrupt EICSS IV bit = 1 (Cause[23]) and,

VEIC bit = 1 (Config3[6])

Source is external interrupt controller.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R-0 R-1 R-1 R-1 U-0 U-0

— — —— HSS[3:0]

23:16 U-0 U-0 R-x R-x R-x R-x U-0 U-0

— — —— EICSS[3:0]

15:8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

ESS[3:0] — — PSS[3:2]

7:0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0

PSS[1:0] — — CSS[3:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-26 HSS[3:0]: High Shadow Set bits

This bit contains the highest shadow set number that is implemented by this processor. A value of ‘0000’ in

these bits indicates that only the normal GPRs are implemented.

1111 = Reserved

0111 = Eight shadow sets are present

0110 = Reserved

0101 = Reserved

0100 = Reserved

0011 = Four shadow sets are present

0010 = Reserved

0001 = Two shadow sets are present

0000 = One shadow set (normal GPR set) is present

The value in this bit also represents the highest value 0], EICSS[3:0], that can be written to the ESS[3:

PSS[3:0], and CSS[3:0] bits of this register, or to any of the bits of the SRSMap register. The operation of

the processor is undefined if a value larger than the one in this bit is written to any of these other bits.

bit 25-22 Unimplemented: Read as ‘0’

bit 21-18 ntroller Shadow SetEICSS[3:0]: External Interrupt Co bits

EIC Interrupt mode shadow set. This bit is loaded from the external interrupt controller for each interrupt

request and is used in place of the SRSMap register to select the current shadow set for the interrupt.

bit 17-16 Unimplemented: Read as ‘0’

bit 15-12 ESS[3:0]: Exception Shadow Set bits

This bit specifies the shadow set to use on entry to Kernel mode caused by any exception other than a

vectored interrupt. The operation of the processor is undefined if software writes a value into this bit that is

greater than the value in the HSS[3:0] bits.

bit 11-10 Unimplemented: Read as ‘0’

Section 50. CPU for Devices with MIPS32® microAp-

bit 9-6 PSS[3:0]: Previous Shadow Set bits

Since GPR shadow registers are implemented, this bit is copied from the CSS bit when an exception or

interrupt occurs. An ERET instruction copies this value back into the CSS bit if the BEV bit (Status[22]) = 0.

This bit is not updated on any exception which sets the ERL bit (Status[2]) to ‘1’ (i.e., Reset, Soft Reset, NMI,

cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with the EXL bit

(Status[1]) = 1, or BEV = 1. This bit is not updated on an exception that occurs while ERL = 1.

The operation of the processor is undefined if software writes a value into this bit that is greater than the

value in the HSS[3:0] bits.

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 CSS[3:0]: Current Shadow Set bits

Since GPR shadow registers are implemented, this bit is the number of the current GPR set. This bit is

updated with a new value on any interrupt or exception, and restored from the PSS bit on an ERET.

Table 50-26 describes the various sources from which the CSS[3:0] bits are updated on an exception or

interrupt.

This bit is not updated on any exception which sets the ERL bit (Status[2]) to ‘1’ (i.e., Reset, Soft Reset, NMI,

cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with EXL bit

(Status[1]) = 1, or BEV = 1. Neither is it updated on an ERET with ERL = 1 or BEV = 1. This bit is not updated

on an exception that occurs while ERL = 1.

The value of the CSS[3:0] bits can be changed directly by software only by writing the PSS[3:0] bits and

executing an ERET instruction.

PIC32 Family Reference Manual

50.13.19 SRSMap: Register (CP0 Register 12, Select 3)

The SRSMap register contains eight 4-bit fields that provide the mapping from a vector number

to the shadow set number to use when servicing such an interrupt. The values from this register

are not used for a non-interrupt exception, or a non-vectored interrupt (IV bit = 0, Cause[23] or

VS[4:0] bit = 0, IntCtl[9:5]). In such cases, the shadow set number comes from the ESS[3:0] bits

(SRSCtl[15:12]).

If the HSS[3:0] bits (SRSCTL29:26) are ‘0’, the results of a software read or write of this register

are unpredictable.

The operation of the processor is undefined if a value is written to any bit in this register that is

greater than the value of the HSS[3:0] bits.

The SRSMap register contains the shadow register set numbers for vector numbers 7-0. The

same shadow set number can be established for multiple interrupt vectors, creating a

many-to-one mapping from a vector to a single shadow register set number.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV7[3:0] SSV6[3:0]

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV5[3:0] SSV4[3:0]

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV3[3:0] SSV2[3:0]

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV1[3:0] SSV0[3:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 SSV7[3:0]: Shadow Set Vector 7 bits

Shadow register set number for Vector Number 7.

bit 27-24 SSV6[3:0]: Shadow Set Vector 6 bits

Shadow register set number for Vector Number 6.

bit 23-20 SSV5[3:0]: Shadow Set Vector 5 bits

Shadow register set number for Vector Number 5.

bit 19-16 SSV4[3:0]: Shadow Set Vector 4 bits

Shadow register set number for Vector Number 4.

bit 15-12 SSV3[3:0]: Shadow Set Vector 3 bits

Shadow register set number for Vector Number 3.

bit 11-8 SSV2[3:0]: Shadow Set Vector 2 bits

Shadow register set number for Vector Number 2.

bit 7-4 SSV1[3:0]: Shadow Set Vector 1 bits

Shadow register set number for Vector Number 1.

bit 3-0 SSV0[3:0]: Shadow Set Vector 0 bit

Shadow register set number for Vector Number 0.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.20 View_IPL Register (CP0 Register 12, Select 4)

This register gives read and write access to the IPL[7:0] bits that are also available in the Status

extracting/inserting that field from/to the Status register.

The IPL field is located in non-contiguous bits within the Status register. All of the IPL bits are

presented as a contiguous field within this register.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — IPL[7:6]

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

IPL[5:0] — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-10 Unimplemented: Read as ‘0’

bit 9-2 IPL[7:0]: These bits contain the encoded (0...256) value of the current IPL.

bit 1-0 Unimplemented: Read as ‘0’

Section 50. CPU for Devices with MIPS32® microAp-

50.13.22 Cause Register (CP0 Register 13, Select 0)

The Cause register primarily describes the cause of the most recent exception. In addition, bits

also control software interrupt requests and the vector through which interrupts are dispatched.

With the exception of the IP1, IP0, DC, and IV bits, all bits in the Cause register are read-only.

Table 50-27: Cause Register EXCCODE[4:0] Bits

Exception Code Value

Mnemonic Description

Decimal Hex

0 0x00 Int Interrupt

1 0x01 MOD(1) TLB modified exception

2 0x02 TLBL(1) TLB exception (load or instruction fetch)

3 0x03 TLBS(1) TLB exception (store)

4 0x04 AdEL Address error exception (load or instruction fetch)

5 0x05 AdES Address error exception (store)

6 0x06 IBE Bus error exception (instruction fetch)

7 0x07 DBE Bus error exception (data reference: load or store)

8 0x08 Sys Syscall exception

9 0x09 Bp Breakpoint exception

10 0x0a RI Reserved instruction exception

11 0x0B CPU Coprocessor Unusable exception

12 0x0C Ov Arithmetic Overflow exception

13 0x0D Tr Trap exception

14 0x0E — Reserved

15 0x0F FPE(2) Floating Point exception

16-18 0x10-0x0x12 Reserved

19 0x13 TLBRI(1)I TLB read-inhibit

20 0x14 TLBEI

(1) TLB execute-inhibit

21-22 0x15-0x16 — Reserved

23 0x17 WATCH(1) Reference to WatchHi/WatchLo address

24 0x18 MCheck(1) Machine check

25 0x19 — Reserved

26 0x1A DSPDis DSP ASE state disabled exception

(3)

27-31 0x1B-0x1F — Reserved

Note 1: This feature is only available on PIC32 devices with the MPU core. Refer to the

“CPU” chapter in the specific device data sheet for availability.

2: This feature is only available on PIC32 devices with the M-Class core. Refer to the

“FPU” chapter in the specific device data sheet to determine availability.

3: DSP ASE is not available on all devices. Please consult the “CPU” chapter of the

specific device data sheet to determine availability

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R/W-0 R-0 R-x R-x

BD TI CE[1:0] DC PCI IC AP

23:16 R/W-x R/W-x R-x U-0 U-0 U-0 R-x R-x

IV WP(1) FDCI — — — RIPL[7:6]

15:8 R-x R-x R-x R-x R-x R-x R/W-x R/W-x

RIPL[5:0] IP1 IP0

7:0 U-0 R-x R-x R-x R-x R-x U-0 U-0

— EXCCODE[4:0] — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 BD: Branch Delay bit

Indicates whether the last exception taken occurred in a branch delay slot:

1 = In delay slot

0 = Not in delay slot

The processor updates BD only if the EXL bit (Status[1]) was ‘0’ when the exception occurred.

bit 30 TI: Timer Interrupt bit

Timer Interrupt. This bit denotes whether a timer interrupt is pending (analogous to the IP bits for other

interrupt types):

1 = Timer interrupt is pending

0 = No timer interrupt is pending

bit 29-28 CE[1:0]: Coprocessor Exception bits

Coprocessor unit number referenced when a Coprocessor Unusable exception is taken. This bit is loaded

by hardware on every exception, but is unpredictable for all exceptions except for Coprocessor Unusable.

11 = Reserved

10 = Reserved

01 = Reserved

00 = Coprocessor 0

bit 27 DC: Disable Count Register bit

In some power-sensitive applications, the Count register is not used and can be stopped to avoid

unnecessary toggling.

1 = Disable counting of Count register

0 = Enable counting of Count register

bit 26 PCI: Performance Counter Interrupt bit

1 = Performance counter interrupt is pending

0 = No performance counter interrupt is pending

bit 25 IC: Interrupt Chaining bit

Indicates if Interrupt chaining occurred on the last IRET instruction.

1 = Interrupt Chaining occurred during last IRET instruction

0 = Interrupt Chaining did not happen on last IRET instruction

bit 24 AP: Interrupt Auto-Prologue Exception bit

Indicates whether an exception occurred during Interrupt Auto-Prologue.

1 = Exception occurred during Auto-Prologue operation

0 = Exception did not occur during Auto-Prologue operation

Note 1: This bit is only available on PIC32 devices with the MPU core. Refer to the “CPU” chapter in the specific

device data sheet for availability.

Section 50. CPU for Devices with MIPS32® microAp-

bit 23 IV: Interrupt Vector bit

Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector

1 = Use the special interrupt vector (0x200)

0 = Use the general exception vector (0x180)

If the IV bit (Cause[23]) is ‘1’ and the BEV bit (Status[22]) is ‘0’, the special interrupt vector represents the

base of the vectored interrupt table.

bit 22 WP: Watch Exception Pending bit(1)

This bit indicates that a watch exception was deferred because the status bits EXL or ERL were set at the

time the watch exception was detected.

1 = Watch exception pending

0 = Watch exception not pending

When set, this bit indicates a pending watch exception, and causes the exception to be initiated once the

Status EXL and ERL bits are both zero. The software must clear this bit as part of the watch exception

handler to prevent a watch exception loop.

Note: Software should not write a '1 0' to this bit when its value is ' ', thereby causing a 0-to-1 transition.

If such a transition is caused by software, the results are unpredictable.

bit 21 FDCI: Fast Debug Channel Interrupt bit

This bit indicates that a FDC interrupt is pending

1 = Fast Debug Channel interrupt is pending

0 = Fast Debug Channel interrupt is not pending

bit 20-18 Unimplemented: Read as ‘0’

bit 17-10 RIPL[7:0]: Requested Interrupt Priority Level bits

This bit is the encoded (255-0) value of the requested interrupt. A value of ‘0’ indicates that no interrupt is

requested.

bit 9-8 IP[1:0]: Software Interrupt Request Control bits

Controls the request for software interrupts

1 = Request software interrupt

0 = No interrupt requested

These bits are exported to the system interrupt controller for prioritization in EIC Interrupt mode with other

interrupt sources.

bit 7 Unimplemented: Read as ‘0’

bit 6-2 EXCCODE[4:0]: Exception Code bits

refer to the Table 50-27 for the list of Exception codes.

bit 1-0 Unimplemented: Read as ‘0’

Note 1: This bit is only available on PIC32 devices with the MPU core. Refer to the “CPU” chapter in the specific

device data sheet for availability.

PIC32 Family Reference Manual

50.13.23 View_RIPL Register (CP0 Register 13, Select 4)

This register gives read access to the RIPL bit that is also available in the Cause register. This

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0

— — — — — — RIPL[7:6]

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 R/W-0

RIPL[5:0] IP[1:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-10 Unimplemented: Read as ‘0’

bit 9-2 RIPL[7:0]: Requested Interrupt Priority Level bits

If EIC Interrupt mode is enabled, this bit indicates the encoded (0...255) value of the current Requested Priority

Level of the pending interrupt.

bit 1-0 IP[1:0]: Software Interrupt Pending bits

If EIC Interrupt mode is not enabled, controls which SW interrupts are pending.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.24 NestedExc Register (CP0 Register 13, Select 5)

The NestedExc register is a read-only register that contains the values of Status[1] (EXL) and

Status[2] (ERL) prior to acceptance of the current exception.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x U-0

— — — — —— NERL NEXL

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2 NERL: Nested Error Level bit

This bit contains the value of the ERL bit prior to acceptance of the current exception. This bit is updated by

all exceptions that would set either the EXL bit or the ERL bit in the status register. This bit is not updated by

Debug exceptions.

bit 1 NEXL: Nested Exception Level bit

This bit contains the value of the EXL bit prior to acceptance of current exception. This bit is updated by

exceptions that would update the exception program counter if the EXL bit is not set (MCheck, interrupt,

Address Error, all TLB exceptions, Bus Error, CopUnusable, Reserved Instruction, Overflow, Trap, Syscall,

FPU, etc.). For these exception types, this register field is updated regardless of the value of StatusEXL. This

bit is not updated by exception types that update ErrorEPC (Reset, Soft Reset, NMI, and Cache Error). In

addition, this bit is not updated by Debug exceptions.

bit 0 Unimplemented: Read as ‘0’

PIC32 Family Reference Manual

50.13.25 EPC Register (CP0 Register 14, Select 0)

The Exception Program Counter (EPC) is a read/write register that contains the address at which

processing resumes after an exception has been serviced. All bits of the EPC register are

significant and are writable.

For synchronous (precise) exceptions, the EPC contains one of the following:

• The virtual address of the instruction that was the direct cause of the exception

• The virtual address of the immediately preceding BRANCH JUMP or instruction, when the

exception causing instruction is in a branch delay slot and the Branch Delay bit in the

Cause register is set

On new exceptions, the processor does not write to the EPC register when the EXL bit in the

Status register is set; however, the register can still be written through the MTC0 instruction.

Since the PIC32 family implements MIPS16e® or microMIPS ASE, a read of the EPC register

(via MFC0) returns the following value in the destination GPR:

GPR[rt] ExceptionPC31..1 || ISAMode0

That is, the upper 31 bits of the exception PC are combined with the lower bit of the ISA[1:0] bits

(Config3[15:14]) and are written to the GPR.

Similarly, a write to the EPC register (via MTC0) takes the value from the GPR and distributes

that value to the exception PC and the ISA[1:0] bits (Config3[15:14]), as follows:

ExceptionPC GPR[rt]31..1 || 0

ISAMode 2#0 || GPR[rt]0

That is, the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC, and the

lower bit of the exception PC is cleared. The upper bit of the ISA[1:0] bits (Config3[15:14]) is

cleared and the lower bit is loaded from the lower bit of the GPR.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[31:24]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[23:16]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[15:8]

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 EPC[31:0]: Exception Program Counter bits

Section 50. CPU for Devices with MIPS32® microAp-

50.13.26 NestedEPC Register (CP0 Register 14, Select 2)

The NestedEPC register is a read/write register with the same behavior as the EPC register, with

the following exceptions:

• The NestedEPC register ignores the value of Status[1] (EXL) and is therefore updated on

the occurrence of any exception, including nested exceptions

• The NestedEPC register is not used by the ERET DERET IERET/ / instructions. To return to

the address stored in NestedEPC, software must copy the value of the NestedEPC register

to the EPC register.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[31:24]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[23:16]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[15:8]

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 EPC[31:0]: Nested Exception Program Counter bits

These bits are updated by exceptions that would update the exception program counter if the EXL bit is not

set (MCheck, Interrupt, Address Error, all TLB exceptions, Bus Error, CopUnusable, Reserved Instruction,

Overflow, Trap, Syscall, FPU, etc.). For these exception types, this register field is updated regardless of the

value of EXL. These bits are not updated by exception types that update the exception program counter

(Reset, Soft Reset, NMI, and Cache Error). In addition, these bits are not updated by Debug exceptions.

PIC32 Family Reference Manual

50.13.27 PRID Register (CP0 Register 15, Select 0)

The Processor Identification (PRID) register is a 32-bit read-only register that contains informa-

tion identifying the manufacturer, manufacturer options, processor identification, and revision

level of the processor.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-1

COMPANYID[23:16]

15:8 R-1 R-0 R-0 R-1 R-1 R-1 R-1 R-0

PROCESSORID[15:8]

7:0 R-x R-x R-x R-x R-x R-x R-x R-x

MAJORREV[2:0] MINORREV[2:0] PATCHREV[1:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 COMPANYID[23:16]: Company Identification bits

In PIC32 devices, these bits contain a value of ‘1’ to indicate Imagination Technologies Ltd. as the

processor manufacturer/designer.

bit 15-8 PROCESSORID[15:8]: Processor Identification bits

These bits allow software to distinguish between the various types of Imagination Technologies Ltd.

processors.

0x9E = Microprocessor core

bit 7-5 MAJORREV[2:0]: Processor Major Revision Identification bits

These bits allow software to distinguish between one revision and another of the same processor type. This

number is increased on major revisions of the processor core.

bit 4-2 MINORREV[2:0]: Processor Minor Revision Identification bits

This number is increased on each incremental revision of the processor and reset on each new major

revision.

bit 1-0 PATCHREV[1:0]: Processor Patch Level Identification bits

If a patch is made to modify an older revision of the processor, the value of these bits will be incremented.

Section 50. CPU for Devices with MIPS32® microAp-

50.13.28 Ebase Register (CP0 Register 15, Select 1)

The Ebase register is a read/write register containing the base address of the exception vectors

used when the BEV bit (Status[22]) equals ‘0’, and a read-only CPU number value that may be

used by software to distinguish different processors in a multi-processor system.

The Ebase register provides the ability for software to identify the specific processor within a

multi-processor system, and allows the exception vectors for each processor to be different,

especially in systems composed of heterogeneous processors. Bits 31-12 of the Ebase register

are concatenated with zeros to form the base of the exception vectors when the BEV bit is ‘0’.

The exception vector base address comes from the fixed defaults when the BEV bit is ‘1’, or for

any EJTAG Debug exception. The Reset state of bits 31-12 of the Ebase register initialize the

exception base register to 0x80000000.

Bits 31 and 30 of the Ebase Register are fixed with the value 2#10 to force the exception base

address to be in the kseg0 or kseg1 unmapped virtual address segments.

If the value of the exception base register is to be changed, this must be done with the BEV bit

equal to ‘ ’. The operation of the proces1sor is undefined if the Ebase[17:0] bits are written with a

different value when the BEV bit (Status[22]) is ‘0’.

Combining bits 31-20 of the Ebase register allows the base address of the exception vectors to

be placed at any 4 KB page boundary.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EBASE[17:12]

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EBASE[11:4]

15:8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0

EBASE[3:0] — — CPUNUM[9:8]

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CPUNUM[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as ‘1’

bit 30 Unimplemented: Read as ‘0’

bit 29-12 EBASE[17:0]: Exception Vector Base Address bits

In conjunction with bits 31-30, these bits specify the base address of the exception vectors when the BEV

bit (Status[22]) is ‘0’.

bit 11-10 Unimplemented: Read as ‘0’

bit 9-0 CPUNUM[9:0]: CPU Number bits

These bits specify the number of CPUs in a multi-processor system and can be used by software to

distinguish a particular processor from others. In a single processor system, this value is set to ‘0’.

PIC32 Family Reference Manual

50.13.29 CDMMBase Register (CP0 Register 15, Select 2)

The 36-bit physical base address for the Common Device Memory Map (CDMM) is defined by

this register. Since the PIC32 is a 32-bit device, the upper four bits of the address are zero. The

CDMM is a region of physical address space that is reserved for mapping I/O device

Configuration registers within a MIPS processor. The CDMM helps aggregate various device

mappings into one area, preventing fragmentation of the memory address space. On PIC32

devices, the CDMM contains the Fast Debug Channel (FDC) control registers.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

CDMMUA[20:13]

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

CDMMUA[12:5]

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-0 R-0 R-0

CDMMUA[4:0] EN CI CDMMSize[8]

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-1 R-0

CDMMSize[7:0]

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 CDMMUA[20:0]: CDMM Upper Address bits

Bits 35-15 of the base physical address of the memory mapped registers. Unimplemented bits ignore writes

and return ‘0’ on reads.

bit 10 EN: CDMM Enable bit

1 = CDMM region is enabled

0 = CDMM region is disabled

bit 9 CI: Device Register Block Reserved bit

1 = The first 64-byte Device Register Block of the CDMM is reserved for additional registers that manage

CDMM region behavior and are not IO device registers

0 = The first 64-byte Device Register Block of the CDMM is not reserved

bit 8-0 CDMMSize[8:0]: CDMM Size bits

These bits indicate the number of cks instantiated in the CPU core. 64-byte Device Register Blo

111111111 = 512 Device Register Blocks

•

000000000 = 1 Device Register Block

Section 50. CPU for Devices with MIPS32® microAp-

50.13.30 Config Register (CP0 Register 16, Select 0)

The Config register specifies various configuration and capabilities information. Most of the fields

in the Config register are initialized by hardware during the Reset exception process, or are

constant.

Note: The Core Configuration register bit fields and default values may vary between

devices. Refer to the “Core Configuration” chapter in the specific device data

sheet for the core configuration of a specific device.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R-x

— K23[2:0](1) KU[2:0](1) ISP

23:16

R-x R-x R-x R-x U-0 R-x R-x R-x

DSP UDI SB MDU — MM[1:0](2) DS(1)

(2)

15:8 R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-x

BE AT[1:0] AR[2:0] MT[2:1]

7:0 R-x U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

MT[0] — — — — K0[2:0]

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.

bit 30-28 K23[2:0]: kseg2 and kseg3 bits(1)

These bits control the cacheability of the kseg2 and kseg3 address segments.

Refer to Table 50-28 for the bit encoding.

bit 27-25 KU[2:0]: kuseg and useg bits(1)

These bits control the cacheability of the kuseg and useg address segments.

Refer to Table 50-28 for the bit encoding.

bit 24 ISP: Instruction Scratchpad RAM bit

This bit indicates whether instruction scratchpad RAM is implemented.

1 = Instruction scratchpad RAM is implemented

0 = Instruction scratchpad RAM is not implemented

bit 23 DSP: Data Scratchpad RAM bit

This bit indicates whether data scratchpad RAM is implemented.

1 = Data scratchpad RAM is implemented

0 = Data scratchpad RAM is not implemented

Note 1: This bit is only available on devices with the MCU Microprocessor core. On devices with the MPU

Microprocessor core, this bit is reserved, and is always read as ‘0’. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

2: This bit is only available on devices with the MPU Microprocessor core. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

PIC32 Family Reference Manual

bit 22 UDI: User-defined bit

This bit indicates that CorExtend User-Defined Instructions have been implemented.

1 = User-defined instructions are implemented

0 = No user-defined instructions are implemented

bit 21 SB: SimpleBE bit

This bit indicates whether SimpleBE Bus mode is enabled.

1 = Only simple byte enables allowed on internal bus interface

0 = No reserved byte enables on internal bus interface

This bit is hardwired to ‘1’ to indicate only simple byte enables allowed on internal bus interface.

bit 20 MDU: Multiply/Divide Unit bit

1 = Iterative, area-efficient MDU

0 = Fast, high-performance MDU

This bit is hardwired to ‘0’ to indicate the fast, high-performance MDU.

bit 19 Unimplemented: Read as ‘0’

bit 18-17 MM[1:0]: Merge Mode bits(2)

11 = Reserved

10 = Merging is allowed

01 = Reserved

00 = Merging is not allowed

bit 16 DS: Dual SRAM bit(1)

1 = Dual instruction/data SRAM internal bus interfaces

0 = Unified instruction/data SRAM internal bus interface

BM: Burst Mode bit(2)

This bit is hardwired to a ‘0’ to indicate burst order is sequential.

bit 15 BE: Big-Endian bit

Indicates the endian mode in which the processor is running, PIC32 is always little-endian.

1 = Big-endian

0 = Little-endian

bit 14-13 AT[1:0]: Architecture Type bits

Architecture type implemented by the processor. This bit is always ‘00’ to indicate the MIPS32 architecture.

bit 12-10 AR[2:0]: Architecture Revision Level bits

Architecture revision level. This bit is always ‘001’ to indicate MIPS32 Release 2.

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = Reserved

010 = Reserved

001 = Release 2

000 = Release 1

Note 1: This bit is only available on devices with the MCU Microprocessor core. On devices with the MPU

Microprocessor core, this bit is reserved, and is always read as ‘0’. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

2: This bit is only available on devices with the MPU Microprocessor core. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

Section 50. CPU for Devices with MIPS32® microAp-

bit 9-7 MT[2:0]: MMU Type bits

PIC32 devices with the MCU Microprocessor core use a fixed-mapping MMU.

PIC32 devices with the MPU Microprocessor core use a TLB-based MMU.

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = Fixed mapping

010 = Reserved

001 = Standard TLB

000 = Reserved

bit 6-3 Unimplemented: Read as ‘0’

bit 2-0 K0[2:0]: Kseg0 bits

Kseg0 coherency algorithm. Refer to Table 50-28 for the bit encoding.

Note 1: This bit is only available on devices with the MCU Microprocessor core. On devices with the MPU

Microprocessor core, this bit is reserved, and is always read as ‘0’. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

2: This bit is only available on devices with the MPU Microprocessor core. Refer to the “CPU” chapter in the

specific device data sheet to determine availability.

Table 50-28: Cache Coherency Attributes

K0[2:0] Value Cache Coherency Attribute

011 Cacheable, non-coherent, write-back, write allocate

010 Uncached

001 Cacheable, non-coherent, write-through, write allocate

000 Cacheable, non-coherent, write-through, no write allocate

Section 50. CPU for Devices with MIPS32® microAp-

bit 18-16 IA[2:0]: Instruction-Cache Associativity bits(1)

Contains the level of instruction cache associativity.

0x0 = Direct-mapped

0x1 = 2-way

0x2 = 3-way

0x3 = 4-way

0x4 = Reserved

0x5 = Reserved

0x6 = Reserved

0x7 = Reserved

bit 15-13 DS[2:0]: Data-Cache Sets bits(1)

Contains the number of data cache sets per way.

0x0 = 64

0x1 = 128

0x2 = 256

0x3 = 512

0x4 = 1024

0x5 = Reserved

0x6 = Reserved

0x7 = Reserved

bit 12-10 DL[2:0]: Data-Cache Line bits(1)

Contains the data cache line size.

0x0 = No instruction cache is present

0x3 = 16 bytes

All other values are Reserved.

bit 9-7 DA[2:0]: Data-Cache Associativity bits(1)

Contains the type of set associativity for the data cache.

0x0 = Direct-mapped

0x1 = 2-way

0x2 = 3-way

0x3 = 4-way

0x4 = Reserved

0x5 = Reserved

0x6 = Reserved

0x7 = Reserved

bit 6-5 Unimplemented: Read as ‘0’

bit 4 PC: Performance Counter bit

Performance Counter registers implemented.

1 = The processor core contains Performance Counters

0 = The processor core does not contain Performance Counters

bit 3 WR: Watch Register Presence bit

1 = No Watch registers are present

0 = One or more Watch registers is present

bit 2 CA: Code Compression Implemented bit

1 = MIPS16e is implemented

0 = No MIPS16e present

bit 1 EP: EJTAG Present bit

1 = EJTAG unit is implemented

0 = EJTAG unit is not implemented

bit 0 FP: Floating Point Unit bit

1 = Floating Point Unit is implemented

0 = Floating Point Unit is not implemented

Note 1: For the PIC32 devices with the MCU Microprocessor core, these bits are reserved and always read as ‘0’.

Refer to the “CPU” chapter in the specific device data sheet to determine availability.

PIC32 Family Reference Manual

50.13.32 Config2 (CP0 Register 16, Select 2)

The Config2 register is an adjunct to the Config register and is reserved to encode additional

capabilities information. Config2 is allocated for showing the configuration of level 2/3 caches.

These bits are reset to ‘0’ because L2/L3 caches are not supported by the PIC32 core. All bits in

the Config2 register are read-only.

Note: The Core Configuration register bit fields and default values may vary between

devices. Refer to the “Core Configuration” chapter in the specific device data

sheet for the core configuration of a specific device.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config3 register.

bit 30-0 Unimplemented: Read as ‘0’

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