Microchip AT90USB646 Manual


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AVR® Instruction Set Manual
AVR® Instruction Set Manual
Introduction
This manual gives an overview and explanation of every instruction available for 8-bit AVR
® devices. Each instruction
has its own section containing functional description, it’s opcode, and syntax, the end state of the status register, and
cycle times.
The manual also contains an explanation of the different addressing modes used by AVR devices and an appendix
listing all modern AVR devices and what instruction it has available.
© 2021 Microchip Technology Inc. Manual DS40002198B-page 1
Table of Contents
Introduction.....................................................................................................................................................1
1. Instruction Set Nomenclature..................................................................................................................6
2. CPU Registers Located in the I/O Space................................................................................................8
2.1. RAMPX, RAMPY, and RAMPZ.....................................................................................................8
2.2. RAMPD........................................................................................................................................ 8
2.3. EIND.............................................................................................................................................8
3. The Program and Data Addressing Modes.............................................................................................9
3.1. Register Direct, Single Register Rd..............................................................................................9
3.2. Register Direct - Two Registers, Rd and Rr................................................................................. 9
3.3. I/O Direct.................................................................................................................................... 10
3.4. Data Direct................................................................................................................................. 10
3.5. Data Indirect............................................................................................................................... 11
3.6. Data Indirect with Pre-decrement............................................................................................... 11
3.7. Data Indirect with Post-increment.............................................................................................. 12
3.8. Data Indirect with Displacement.................................................................................................12
3.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions............. 13
3.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction................. 13
3.11. Store Program Memory Post-increment.....................................................................................14
3.12. Direct Program Addressing, JMP and CALL.............................................................................. 14
3.13. Indirect Program Addressing, IJMP and ICALL..........................................................................15
3.14. Extended Indirect Program Addressing, EIJMP and EICALL.....................................................15
3.15. Relative Program Addressing, RJMP and RCALL..................................................................... 16
4. Conditional Branch Summary............................................................................................................... 17
5. Instruction Set Summary.......................................................................................................................18
6. Instruction Description...........................................................................................................................24
6.1. ADC – Add with Carry................................................................................................................ 24
6.2. ADD – Add without Carry........................................................................................................... 25
6.3. ADIW – Add Immediate to Word................................................................................................ 26
6.4. AND – Logical AND....................................................................................................................27
6.5. ANDI – Logical AND with Immediate..........................................................................................28
6.6. ASR – Arithmetic Shift Right...................................................................................................... 29
6.7. BCLR – Bit Clear in SREG......................................................................................................... 30
6.8. BLD – Bit Load from the T Bit in SREG to a Bit in Register....................................................... 31
6.9. BRBC – Branch if Bit in SREG is Cleared..................................................................................32
6.10. BRBS – Branch if Bit in SREG is Set......................................................................................... 33
6.11. BRCC – Branch if Carry Cleared................................................................................................34
6.12. BRCS – Branch if Carry Set....................................................................................................... 35
6.13. BREAK – Break..........................................................................................................................36
6.14. BREQ – Branch if Equal.............................................................................................................36
6.15. BRGE – Branch if Greater or Equal (Signed).............................................................................37
6.16. BRHC – Branch if Half Carry Flag is Cleared.............................................................................38
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6.17. BRHS – Branch if Half Carry Flag is Set.................................................................................... 39
6.18. BRID – Branch if Global Interrupt is Disabled............................................................................ 40
6.19. BRIE – Branch if Global Interrupt is Enabled............................................................................. 41
6.20. BRLO – Branch if Lower (Unsigned).......................................................................................... 42
6.21. BRLT – Branch if Less Than (Signed)........................................................................................43
6.22. BRMI – Branch if Minus..............................................................................................................44
6.23. BRNE – Branch if Not Equal...................................................................................................... 45
6.24. BRPL – Branch if Plus................................................................................................................46
6.25. BRSH – Branch if Same or Higher (Unsigned).......................................................................... 47
6.26. BRTC – Branch if the T Bit is Cleared........................................................................................48
6.27. BRTS – Branch if the T Bit is Set............................................................................................... 49
6.28. BRVC – Branch if Overflow Cleared.......................................................................................... 50
6.29. BRVS – Branch if Overflow Set..................................................................................................51
6.30. BSET – Bit Set in SREG............................................................................................................ 52
6.31. BST – Bit Store from Bit in Register to T Bit in SREG................................................................53
6.32. CALL – Long Call to a Subroutine..............................................................................................54
6.33. CBI – Clear Bit in I/O Register....................................................................................................55
6.34. CBR – Clear Bits in Register...................................................................................................... 56
6.35. CLC – Clear Carry Flag..............................................................................................................57
6.36. CLH – Clear Half Carry Flag...................................................................................................... 57
6.37. CLI – Clear Global Interrupt Enable Bit......................................................................................58
6.38. CLN – Clear Negative Flag........................................................................................................ 59
6.39. CLR – Clear Register................................................................................................................. 60
6.40. CLS – Clear Sign Flag................................................................................................................61
6.41. CLT – Clear T Bit........................................................................................................................62
6.42. CLV – Clear Overflow Flag.........................................................................................................62
6.43. CLZ – Clear Zero Flag................................................................................................................63
6.44. COM – One’s Complement........................................................................................................ 64
6.45. CP – Compare............................................................................................................................65
6.46. CPC – Compare with Carry........................................................................................................66
6.47. CPI – Compare with Immediate................................................................................................. 67
6.48. CPSE – Compare Skip if Equal..................................................................................................68
6.49. DEC – Decrement...................................................................................................................... 69
6.50. DES – Data Encryption Standard...............................................................................................71
6.51. EICALL – Extended Indirect Call to Subroutine......................................................................... 72
6.52. EIJMP – Extended Indirect Jump............................................................................................... 73
6.53. ELPM – Extended Load Program Memory.................................................................................73
6.54. EOR – Exclusive OR.................................................................................................................. 75
6.55. FMUL – Fractional Multiply Unsigned........................................................................................ 76
6.56. FMULS – Fractional Multiply Signed.......................................................................................... 77
6.57. FMULSU – Fractional Multiply Signed with Unsigned................................................................79
6.58. ICALL – Indirect Call to Subroutine............................................................................................ 80
6.59. IJMP – Indirect Jump..................................................................................................................81
6.60. IN - Load an I/O Location to Register.........................................................................................82
6.61. INC – Increment......................................................................................................................... 83
6.62. JMP – Jump............................................................................................................................... 84
6.63. LAC – Load and Clear................................................................................................................85
6.64. LAS – Load and Set................................................................................................................... 86
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6.65. LAT – Load and Toggle.............................................................................................................. 86
6.66. LD – Load Indirect from Data Space to Register using X...........................................................87
6.67. LD (LDD) – Load Indirect from Data Space to Register using Y................................................ 89
6.68. LD (LDD) – Load Indirect From Data Space to Register using Z............................................... 90
6.69. LDI – Load Immediate................................................................................................................ 92
6.70. LDS – Load Direct from Data Space.......................................................................................... 93
6.71. LDS (AVRrc) – Load Direct from Data Space............................................................................ 94
6.72. LPM – Load Program Memory................................................................................................... 95
6.73. LSL – Logical Shift Left.............................................................................................................. 96
6.74. LSR – Logical Shift Right........................................................................................................... 97
6.75. MOV – Copy Register................................................................................................................ 98
6.76. MOVW – Copy Register Word................................................................................................... 99
6.77. MUL – Multiply Unsigned......................................................................................................... 100
6.78. MULS – Multiply Signed........................................................................................................... 101
6.79. MULSU – Multiply Signed with Unsigned.................................................................................102
6.80. NEG – Two’s Complement....................................................................................................... 103
6.81. NOP – No Operation................................................................................................................ 104
6.82. OR – Logical OR...................................................................................................................... 105
6.83. ORI – Logical OR with Immediate............................................................................................ 106
6.84. OUT – Store Register to I/O Location...................................................................................... 107
6.85. POP – Pop Register from Stack...............................................................................................108
6.86. PUSH – Push Register on Stack..............................................................................................109
6.87. RCALL – Relative Call to Subroutine....................................................................................... 110
6.88. RET – Return from Subroutine................................................................................................. 111
6.89. RETI – Return from Interrupt.................................................................................................... 112
6.90. RJMP – Relative Jump............................................................................................................. 113
6.91. ROL – Rotate Left trough Carry................................................................................................114
6.92. ROR – Rotate Right through Carry...........................................................................................115
6.93. SBC – Subtract with Carry........................................................................................................116
6.94. SBCI – Subtract Immediate with Carry SBI – Set Bit in I/O Register....................................... 117
6.95. SBI – Set Bit in I/O Register..................................................................................................... 118
6.96. SBIC – Skip if Bit in I/O Register is Cleared............................................................................. 119
6.97. SBIS – Skip if Bit in I/O Register is Set.................................................................................... 120
6.98. SBIW – Subtract Immediate from Word................................................................................... 121
6.99. SBR – Set Bits in Register....................................................................................................... 122
6.100. SBRC – Skip if Bit in Register is Cleared.................................................................................123
6.101. SBRS – Skip if Bit in Register is Set........................................................................................ 124
6.102. SEC – Set Carry Flag...............................................................................................................125
6.103. SEH – Set Half Carry Flag....................................................................................................... 126
6.104. SEI – Set Global Interrupt Enable Bit.......................................................................................127
6.105. SEN – Set Negative Flag......................................................................................................... 128
6.106. SER – Set all Bits in Register...................................................................................................128
6.107. SES – Set Sign Flag................................................................................................................ 129
6.108. SET – Set T Bit........................................................................................................................ 130
6.109. SEV – Set Overflow Flag......................................................................................................... 131
6.110. SEZ – Set Zero Flag.................................................................................................................132
6.111. SLEEP......................................................................................................................................132
6.112. SPM (AVRe) – Store Program Memory....................................................................................133
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6.113. SPM (AVRxm, AVRxt) – Store Program Memory.....................................................................135
6.114. ST – Store Indirect From Register to Data Space using Index X............................................. 136
6.115. ST (STD) – Store Indirect From Register to Data Space using Index Y.................................. 138
6.116. ST (STD) – Store Indirect From Register to Data Space using Index Z...................................140
6.117. STS – Store Direct to Data Space............................................................................................141
6.118. STS (AVRrc) – Store Direct to Data Space.............................................................................. 142
6.119. SUB – Subtract Without Carry..................................................................................................143
6.120. SUBI – Subtract Immediate......................................................................................................144
6.121. SWAP – Swap Nibbles.............................................................................................................145
6.122. TST – Test for Zero or Minus................................................................................................... 146
6.123. WDR – Watchdog Reset.......................................................................................................... 147
6.124. XCH – Exchange......................................................................................................................148
7. Appendix A Device Core Overview..................................................................................................... 149
7.1. Core Descriptions.....................................................................................................................149
7.2. Device Tables...........................................................................................................................150
8. Revision History.................................................................................................................................. 161
8.1. Rev. DS40002198B - 02/2021..................................................................................................161
8.2. Rev. DS40002198A - 05/2020..................................................................................................161
8.3. Rev.0856L - 11/2016................................................................................................................ 161
8.4. Rev.0856K - 04/2016................................................................................................................161
8.5. Rev.0856J - 07/2014................................................................................................................ 161
8.6. Rev.0856I – 07/2010................................................................................................................ 161
8.7. Rev.0856H – 04/2009...............................................................................................................162
8.8. Rev.0856G – 07/2008.............................................................................................................. 162
8.9. Rev.0856F – 05/2008............................................................................................................... 162
The Microchip Website...............................................................................................................................163
Product Change Notification Service..........................................................................................................163
Customer Support...................................................................................................................................... 163
Microchip Devices Code Protection Feature.............................................................................................. 163
Legal Notice............................................................................................................................................... 164
Trademarks................................................................................................................................................ 164
Quality Management System..................................................................................................................... 165
Worldwide Sales and Service.....................................................................................................................166
AVR® Instruction Set Manual
© 2021 Microchip Technology Inc. Manual DS40002198B-page 5
1. Instruction Set Nomenclature
Status Register (SREG)
SREG Status Register
CCarry Flag
ZZero Flag
NNegative Flag
VTwo’s Complement Overflow Flag
SSign Flag
HHalf Carry Flag
TTransfer Bit
IGlobal Interrupt Enable Bit
Registers and Operands
Rd: Destination (and source) register in the Register File
Rr: Source register in the Register File
R: Result after instruction is executed
K: Constant data
k: Constant address
b: Bit position (0..7) in the Register File or I/O Register
s: Bit position (0..7)in the Status Register
X,Y,Z: Indirect Address Register (X=R27:R26, Y=R29:R28, and Z=R31:R30 or X=RAMPX:R27:R26,
Y=RAMPY:R29:R28, and Z=RAMPZ:R31:R30 if the memory is larger than 64 KB)
A: I/O memory address
q: Displacement for direct addressing
UU Unsigned × Unsigned operands
SS Signed × Signed operands
SU Signed × Unsigned operands
Memory Space Identifiers
DS( ) Represents a pointer to address in data space
PS( ) Represents a pointer to address in program space
I/O(A) I/O space address A
I/O(A,b) Bit position b of the byte in I/O space address A
Rd(n) Bit n in register Rd
Operator
×Arithmetic multiplication
AVR® Instruction Set Manual
Instruction Set Nomenclature
© 2021 Microchip Technology Inc. Manual DS40002198B-page 6
+Arithmetic addition
-Arithmetic subtraction
Logical AND
Logical OR
Logical XOR
>> Shift right
<< Shift left
== Comparison
Assignment
Swap
xLogical complement of x (NOT x)
Stack
STACK Stack for return address and pushed registers
SP The Stack Pointer
Flags
Flag affected by instruction
0Flag cleared by instruction
1Flag set by instruction
-Flag not affected by instruction
AVR® Instruction Set Manual
Instruction Set Nomenclature
© 2021 Microchip Technology Inc. Manual DS40002198B-page 7
2. CPU Registers Located in the I/O Space
2.1 RAMPX, RAMPY, and RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on
MCUs with more than 64 KB data space, and constant data fetch on MCUs with more than 64 KB program space.
2.2 RAMPD
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more
than 64 KB data space.
2.3 EIND
Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with
more than 64K words (128 KB) program space.
AVR® Instruction Set Manual
CPU Registers Located in the I/O Space
© 2021 Microchip Technology Inc. Manual DS40002198B-page 8
3. The Program and Data Addressing Modes
The AVR® Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the
program memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This
section describes the various addressing modes supported by the AVR architecture. In the following figures, OP
means the operation code part of the instruction word. To simplify, not all figures show the exact location of the
addressing bits. To generalize, the abstract terms RAMEND and FLASHEND have been used to represent the
highest location in data and program space, respectively.
Note:  Not all addressing modes are present in all devices. Refer to the device specific instruction summary.
3.1 Register Direct, Single Register Rd
Figure 3-1. Direct Single Register Addressing
Rd
OP
The operand is contained in the destination register (Rd).
3.2 Register Direct - Two Registers, Rd and Rr
Figure 3-2. Direct Register Addressing, Two Registers
OP Rr Rd
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 9
Operands are contained in the sources register (Rr) and destination register (Rd). The result is stored in the
destination register (Rd).
3.3 I/O Direct
Figure 3-3. I/O Direct Addressing
OP Rr/Rd A
Operand address A is contained in the instruction word. Rr/Rd specify the destination or source register.
Note:  Some AVR microcontrollers have more peripheral units than can be supported within the 64 locations
reserved in the opcode for I/O direct addressing. The extended I/O memory from address 64 and higher can only be
reached by data addressing, not I/O addressing.
3.4 Data Direct
Figure 3-4. Direct Data Addressing
Data Address
OP Rr/Rd
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register. The LDS instruction uses the RAMPD register to access memory above 64 KB.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 10
3.5 Data Indirect
Figure 3-5. Data Indirect Addressing
X, Y OR Z - POINTER
The operand address is the contents of the X-, Y-, or the Z-pointer. In AVR devices without SRAM, Data Indirect
Addressing is called Register Indirect Addressing.
3.6 Data Indirect with Pre-decrement
Figure 3-6. Data Indirect Addressing with Pre-decrement
X, Y OR Z - POINTER
The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents
of the X-, Y-, or the Z-pointer.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 11
3.7 Data Indirect with Post-increment
Figure 3-7. Data Indirect Addressing with Post-increment
X, Y OR Z - POINTER
The X-, Y-, or the Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or
the Z-pointer before incrementing.
3.8 Data Indirect with Displacement
Figure 3-8. Data Indirect with Displacement
Y OR Z - POINTER
q
OP Rr/Rd
The operand address is the result of the q displacement contained in the instruction word added to the Y- or
Z-pointer. Rd/Rr specify the destination or source register.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 12
3.9 Program Memory Constant Addressing using the LPM, ELPM, and SPM
Instructions
Figure 3-9. Program Memory Constant Addressing
LSb
Z - POINTER
Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. For LPM, the LSb
selects low byte if cleared (LSb == 0) or high byte if set (LSb == 1). For SPM, the LSb should be cleared. If ELPM is
used, the RAMPZ Register is used to extend the Z-register.
3.10 Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction
Figure 3-10. Program Memory Addressing with Post-increment
LSb
Z - POINTER
1
Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. The LSb selects low
byte if cleared (LSb == 0) or high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extend
the Z-register.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 13
3.11 Store Program Memory Post-increment
Figure 3-11. Store Program Memory
Z - POINTER
2
The Z-pointer is incremented by 2 after the operation. Constant byte address is specified by the Z-pointer contents
before incrementing. The 15 MSbs select word address and the LSb should be left cleared.
3.12 Direct Program Addressing, JMP and CALL
Figure 3-12. Direct Program Memory Addressing
OP
PC
k
Program execution continues at the address immediate in the instruction word.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 14
3.13 Indirect Program Addressing, IJMP and ICALL
Figure 3-13. Indirect Program Memory Addressing
PC
Z - REGISTER
Program execution continues at the address contained by the Z-register (i.e., the PC is loaded with the contents of
the Z-register).
3.14 Extended Indirect Program Addressing, EIJMP and EICALL
Figure 3-14. Extended Indirect Program Memory Addressing
PC
Z - REGISTER
EIND
Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded
with the contents of the EIND and Z-register).
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 15
3.15 Relative Program Addressing, RJMP and RCALL
Figure 3-15. Relative Program Memory Addressing
PC
k
OP
Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.
AVR® Instruction Set Manual
The Program and Data Addressing Modes
© 2021 Microchip Technology Inc. Manual DS40002198B-page 16
4. Conditional Branch Summary
One Form Complement Form Comment
Mnemonic
Common
Test
Status
Register Mnemonic
Common
Test
Status
Register
BRGE
Rd ≥ Rr
S == 0 BRLT
Rd < Rr
S == 1 Signed
BRSH C == 0 BRLO C == 1 Unsigned
BRNE Rd ≠ Rr Z == 0 BREQ Rd == Rr Z == 1 Unsigned/Signed
BRBC
-
SREG(s) == 0 BRBS
-
SREG(s) == 1 -
BRCC C == 0 BRCS C == 1 Simple
BRPL N == 0 BRMI N == 1 Simple
BRVC V == 0 BRVS V == 1 Simple
Note:  The Status Register status is a result of the preceding instruction, for further information see instruction
description. If the preceding instruction is CP, CPI, SUB, or SUBI, the branch will occur according to column
‘Common Test’.
AVR® Instruction Set Manual
Conditional Branch Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 17
5. Instruction Set Summary
Several updates of the AVR CPU during its lifetime has resulted in different flavors of the instruction set, especially
for the timing of the instructions. Machine code level of compatibility is intact for all CPU versions with very few
exceptions related to the Reduced Core (AVRrc), though not all instructions are included in the instruction set for all
devices. The table below contains the major versions of the AVR 8-bit CPUs. In addition to the different versions,
there are differences depending on the size of the device memory map. Typically these differences are handled by
a C/EC++ compiler, but users that are porting code should be aware that the code execution can vary slightly in the
number of clock cycles.
Table 5-1. Versions of AVR® 8-bit CPU
Name Description
AVR Original instruction set from 1995
AVRe AVR instruction set extended with the Move Word (MOVW) instruction, and the Load Program
Memory (LPM) instruction has been enhanced. Same timing as AVR.
AVRe+ AVRe instruction set extended with the Multiply (xMULxx) instructions, and if applicable with the
extended range instructions EICALL, EIJMP and ELPM. Same timing as AVR and AVRe. Thus,
tables listing number of clock cycles do not distiguish between AVRe and AVRe+, and use AVRe
to represent both.
AVRxm AVRe+ instruction set extended with the Read Modify Write (RMW) and Data Encryption
Standard (DES) instructions. SPM extended to include SPM Z+2. Significantly different timing
compared to AVR, AVRe, AVRe+.
AVRxt A combination of AVRe+ and AVRxm. Available instructions are the same as AVRe+, but the
timing has been improved compared to AVR, AVRe, AVRe+ and AVRxm.
AVRrc AVRrc has only 16 registers in its register file (R31-R16), and the instruction set is reduced. The
timing is significantly different compared to the AVR, AVRe, AVRe+, AVRxm and AVRxt. Refer to
the instruction set summary for further details.
Table 5-2. Arithmetic and Logic Instructions
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1 1 1 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1 1 1 1
ADIW Rd, K Add Immediate to Word R[d + 1]:Rd R[d + 1]:Rd + K Z,C,N,V,S 2 2 2 N/A
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1 1 1 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1 1 1 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1 1 1 1
SBCI Rd, K Subtract Immediate with
Carry
Rd Rd - K - C Z,C,N,V,S,H 1 1 1 1
SBIW Rd, K Subtract Immediate from
Word
R[d + 1]:Rd R[d + 1]:Rd - K Z,C,N,V,S 2 2 2 N/A
AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1 1 1 1
ANDI Rd, K Logical AND with
Immediate
Rd Rd K Z,N,V,S 1 1 1 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1 1 1 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1 1 1 1
EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1 1 1 1
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 18
...........continued
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
COM Rd One’s Complement Rd 0xFF - Rd Z,C,N,V,S 1 1 1 1
NEG Rd Two’s Complement Rd 0x00 - Rd Z,C,N,V,S,H 1 1 1 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1 1 1 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFFh - K) Z,N,V,S 1 1 1 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1 1 1 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1 1 1 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1 1 1 1
CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1 1 1 1
SER Rd Set Register Rd 0xFF None 1 1 1 1
MUL Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2 2 2 N/A
MULS Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2 2 2 N/A
MULSU Rd,Rr Multiply Signed with
Unsigned
R1:R0 Rd x Rr (SU) Z,C 2 2 2 N/A
FMUL Rd,Rr Fractional Multiply
Unsigned
R1:R0 Rd x Rr<<1 (UU) Z,C 2 2 2 N/A
FMULS Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2 2 2 N/A
FMULSU Rd,Rr Fractional Multiply Signed
with Unsigned
R1:R0 Rd x Rr<<1 (SU) Z,C 2 2 2 N/A
DES K Data Encryption if (H == 0), R15:R0
if (H == 1), R15:R0
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
N/A 1 / 2 N/A N/A
Table 5-3. Change of Flow Instructions
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
RJMP k Relative Jump PC PC + k + 1 None 2 2 2 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z
0
None 2 2 2 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z
EIND
None 2 2 2 N/A
JMP k Jump PC k None 3 3 3 N/A
RCALL k Relative Call Subroutine PC PC + k + 1 None 3 / 4
(1) 2 / 3 (1) 2 / 3 3
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
Z
0
None 3 / 4(1) 2 / 3 (1) 2 / 3 3
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
Z
EIND
None 4(1) 3(1) 3 N/A
CALL k Call Subroutine PC k None 4 / 5
(1) 3/ 4 (1) 3 /4 N/A
RET Subroutine Return PC STACK None 4 / 5
(1) 4 / 5 (1) 4 / 5 6
RETI Interrupt Return PC STACK I 4 / 5
(1) 4 / 5 (1) 4 / 5 6
CPSE Rd,Rr Compare, skip if Equal if (Rd == Rr) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1 1 1 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 1 1 1
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 19
...........continued
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1 1 1 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) == 0) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) == 1) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) == 0) PC PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) == 1) PC PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
BRBS s, k Branch if Status Flag Set if (SREG(s) == 1) then
PC
PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) == 0) then
PC
PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BREQ k Branch if Equal if (Z == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRNE k Branch if Not Equal if (Z == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCS k Branch if Carry Set if (C == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCC k Branch if Carry Cleared if (C == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRSH k Branch if Same or Higher if (C == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRLO k Branch if Lower if (C == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRMI k Branch if Minus if (N == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRPL k Branch if Plus if (N == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRGE k Branch if Greater or Equal,
Signed
if (S == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 /2
BRLT k Branch if Less Than, Signed if (S == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRHS k Branch if Half Carry Flag Set if (H == 1) then PC PC + k + 1 None 1 / 2 1 /2 1 / 2 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTS k Branch if T Bit Set if (T == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTC k Branch if T Bit Cleared if (T == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVS k Branch if Overflow Flag is Set if (V == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVC k Branch if Overflow Flag is
Cleared
if (V == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRIE k Branch if Interrupt Enabled if (I == 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRID k Branch if Interrupt Disabled if (I == 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
Table 5-4. Data Transfer Instructions
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
MOV Rd, Rr Copy Register Rd Rr None 1 1 1 1
MOVW Rd, Rr Copy Register Pair R[d + 1]:Rd R[r + 1]:Rr None 1 1 1 N/A
LDI Rd, K Load Immediate Rd K None 1 1 1 1
LDS Rd, k Load Direct from Data Space Rd DS(k) None 2
(1) 3(1)(3) 3(2) 2
LD Rd, X Load Indirect Rd DS(X) None 2
(1) 2(1)(3) 2(2) 1 / 2
LD Rd, X+ Load Indirect and Post-Increment Rd
X
DS(X)
X + 1
None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -X Load Indirect and Pre-Decrement X
Rd
X - 1
DS(X)
None 2(1) 3(1)(3) 2(2) 2 / 3
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 20
...........continued
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
LD Rd, Y Load Indirect Rd DS(Y) None 2
(1) 2(1)(3) 2(2) 1 / 2
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
DS(Y)
Y + 1
None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
Y - 1
DS(Y)
None 2(1) 3(1)(3) 2(2) 2 / 3
LDD Rd, Y+q Load Indirect with Displacement Rd DS(Y + q) None 2
(1) 3(1)(3) 2(2) N/A
LD Rd, Z Load Indirect Rd DS(Z) None 2
(1) 2(1)(3) 2(2) 1 / 2
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
DS(Z)
Z+1
None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
Z - 1
DS(Z)
None 2(1) 3(1)(3) 2(2) 2 / 3
LDD Rd, Z+q Load Indirect with Displacement Rd DS(Z + q) None 2
(1) 3(1)(3) 2(2) N/A
STS k, Rr Store Direct to Data Space DS(k) Rd None 2
(1) 2(1) 2(2) 1
ST X, Rr Store Indirect DS(X) Rr None 2
(1) 1(1) 1(2) 1
ST X+, Rr Store Indirect and Post-Increment DS(X)
X
Rr
X + 1
None 2(1) 1(1) 1(2) 1
ST -X, Rr Store Indirect and Pre-Decrement X
DS(X)
X - 1
Rr
None 2(1) 2(1) 1(2) 2
ST Y, Rr Store Indirect DS(Y) Rr None 2
(1) 1(1) 1(2) 1
ST Y+, Rr Store Indirect and Post-Increment DS(Y)
Y
Rr
Y + 1
None 2(1) 1(1) 1(2) 1
ST -Y, Rr Store Indirect and Pre-Decrement Y
DS(Y)
Y - 1
Rr
None 2(1) 2(1) 1(2) 2
STD Y+q, Rr Store Indirect with Displacement DS(Y + q) Rr None 2
(1) 2(1) 1(2) N/A
ST Z, Rr Store Indirect DS(Z) Rr None 2
(1) 1(1) 1(2) 1
ST Z+, Rr Store Indirect and Post-Increment DS(Z)
Z
Rr
Z + 1
None 2(1) 1(1) 1(2) 1
ST -Z, Rr Store Indirect and Pre-Decrement Z
DS(Z)
Z - 1
Rr
None 2(1) 2(1) 1(2) 2
STD Z+q,Rr Store Indirect with Displacement DS(Z + q) Rr None 2
(1) 2(1) 1(2) N/A
LPM Load Program Memory R0 PS(Z) None 3 3 3 N/A
LPM Rd, Z Load Program Memory Rd PS(Z) None 3 3 3 N/A
LPM Rd, Z+ Load Program Memory and Post-
Increment
Rd
Z
PS(Z)
Z + 1
None 3 3 3 N/A
ELPM Extended Load Program Memory R0 PS(RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z Extended Load Program Memory Rd PS(RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z+ Extended Load Program Memory
and Post-Increment
Rd
(RAMPZ:Z)
PS(RAMPZ:Z)
(RAMPZ:Z) + 1
None 3 3 3 N/A
SPM Store Program Memory PS(RAMPZ:Z) R1:R0 None -(4) -(4) -(4) N/A
SPM Z+ Store Program Memory and Post-
Increment by 2
PS(RAMPZ:Z)
Z
R1:R0
Z + 2
None N/A - (4) -(4) N/A
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 21
...........continued
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
IN Rd, A In From I/O Location Rd I/O(A) None 1 1 1 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1 1 1 1
PUSH Rr Push Register on Stack STACK Rr None 2 1
(1) 1 1
POP Rd Pop Register from Stack Rd STACK None 2 2
(1) 2 3
XCH Z, Rd Exchange DS(Z) Rd None N/A 2 N/A N/A
LAS Z, Rd Load and Set DS(Z)
Rd
Rd v DS(Z)
DS(Z)
None N/A 2 N/A N/A
LAC Z, Rd Load and Clear DS(Z)
Rd
(0xFF – Rd) DS(Z)
DS(Z)
None N/A 2 N/A N/A
LAT Z, Rd Load and Toggle DS(Z)
Rd
Rd DS(Z)
DS(Z)
None N/A 2 N/A N/A
Table 5-5. Bit and Bit-Test Instructions
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
LSL Rd Logical Shift Left C
Rd(n+1)
Rd(0)
Rd(7)
Rd(n), n=6...0
0
Z,C,N,V,H 1 1 1 1
LSR Rd Logical Shift Right C
Rd(n)
Rd(7)
Rd(0)
Rd(n+1), n=0...6
0
Z,C,N,V 1 1 1 1
ROL Rd Rotate Left Through Carry temp
C
Rd(n+1)
Rd(0)
C
Rd(7)
Rd(n), n=6...0
temp
Z,C,N,V,H 1 1 1 1
ROR Rd Rotate Right Through Carry temp
C
Rd(n)
Rd(7)
C
Rd(0)
Rd(n+1), n=0...6
temp
Z,C,N,V 1 1 1 1
ASR Rd Arithmetic Shift Right C
Rd(n)
Rd(7)
Rd(0)
Rd(n+1), n=0..6
Rd(7)
Z,C,N,V 1 1 1 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1 1 1 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 2 1 1 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 2 1 1 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1 1 1 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1 1 1 1
BSET s Flag Set SREG(s) 1 SREG(s) 1 1 1 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1 1 1 1
SEC Set Carry C 1 C 1 1 1 1
CLC Clear Carry C 0 C 1 1 1 1
SEN Set Negative Flag N 1 N 1 1 1 1
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 22
...........continued
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
CLN Clear Negative Flag N 0 N 1 1 1 1
SEZ Set Zero Flag Z 1 Z 1 1 1 1
CLZ Clear Zero Flag Z 0 Z 1 1 1 1
SEI Global Interrupt Enable I 1 I 1 1 1 1
CLI Global Interrupt Disable I 0 I 1 1 1 1
SES Set Sign Bit S 1 S 1 1 1 1
CLS Clear Sign Bit S 0 S 1 1 1 1
SEV Set Two’s Complement Overflow V 1 V 1 1 1 1
CLV Clear Two’s Complement
Overflow
V 0 V 1 1 1 1
SET Set T in SREG T 1 T 1 1 1 1
CLT Clear T in SREG T 0 T 1 1 1 1
SEH Set Half Carry Flag in SREG H 1 H 1 1 1 1
CLH Clear Half Carry Flag in SREG H 0 H 1 1 1 1
Table 5-6. MCU Control Instructions
Mnemonic Operands Description Operation Flags #Clocks
AVRe
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
BREAK Break See the debug interface description None 1 1 1 1
NOP No Operation None 1 1 1 1
SLEEP Sleep See the power management and sleep description None 1 1 1 1
WDR Watchdog Reset See the Watchdog Controller description None 1 1 1 1
Notes: 
1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external
RAM.
2. Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM.
A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent
on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more
information.
3. If the LD instruction is accessing I/O Registers, one cycle can be deducted.
4. Varies with the programming time of the device.
AVR® Instruction Set Manual
Instruction Set Summary
© 2021 Microchip Technology Inc. Manual DS40002198B-page 23
6. Instruction Description
6.1 ADC – Add with Carry
6.1.1 Description
Adds two registers and the contents of the C flag and places the result in the destination register Rd.
Operation:
(i) Rd ← Rd + Rr + C
Syntax: Operands: Program Counter:
(i) ADC Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1
16-bit Opcode:
0001 11rd dddd rrrr
6.1.2 Status Register (SREG) and Boolean Formula
I T H S V N Z C
⇔ ⇔ ⇔ ⇔ ⇔ ⇔
HRd3 Rr3 Rr3 R3 R3 Rd3 ∧ ∨ ∧
Set if there was a carry from bit 3; cleared otherwise.
SN V, for signed tests.
VRd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∧ ∧
Set if two’s complement overflow resulted from the operation; cleared otherwise.
NR7
Set if MSB of the result is set; cleared otherwise.
ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧
Set if the result is ; cleared otherwise.0x00
CRd7 Rr7 Rr7 R7 R7 Rd7 ∧ ∨ ∧
Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result) equals Rd after the operation.
Example:
; Add R1:R0 to R3:R2
add r2,r0 ; Add low byte
adc r3,r1 ; Add with carry high byte
Words 1 (2 bytes)
AVR® Instruction Set Manual
Instruction Description
© 2021 Microchip Technology Inc. Manual DS40002198B-page 24
Table 6-1. Cycles
Name Cycles
AVRe 1
AVRxm 1
AVRxt 1
AVRrc 1
6.2 ADD – Add without Carry
6.2.1 Description
Adds two registers without the C flag and places the result in the destination register Rd.
Operation:
(i) (i) Rd ← Rd + Rr
Syntax: Operands: Program Counter:
(i) ADD Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1
16-bit Opcode:
0000 11rd dddd rrrr
6.2.2 Status Register (SREG) and Boolean Formula
I T H S V N Z C
⇔ ⇔ ⇔ ⇔ ⇔ ⇔
HRd3 Rr3 Rr3 R3 R3 Rd3 ∧ ∨ ∧
Set if there was a carry from bit 3; cleared otherwise.
SN V, for signed tests.
VRd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∧ ∧
Set if two’s complement overflow resulted from the operation; cleared otherwise.
NR7
Set if MSB of the result is set; cleared otherwise.
ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧
Set if the result is ; cleared otherwise.0x00
CRd7 Rr7 Rr7 R7 R7 Rd7 ∧ ∨ ∧
Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result) equals Rd after the operation.
AVR® Instruction Set Manual
Instruction Description
© 2021 Microchip Technology Inc. Manual DS40002198B-page 25
Example:
add r1,r2 ; Add r2 to r1 (r1=r1+r2)
add r28,r28 ; Add r28 to itself (r28=r28+r28)
Words 1 (2 bytes)
Table 6-2. Cycles
Name Cycles
AVRe 1
AVRxm 1
AVRxt 1
AVRrc 1
6.3 ADIW – Add Immediate to Word
6.3.1 Description
Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates
on the upper four register pairs and is well suited for operations on the Pointer Registers.
This instruction is not available on all devices. Refer to .
Appendix A
Operation:
(i) R[d+1]:Rd ← R[d+1]:Rd + K
Syntax: Operands: Program Counter:
(i) ADIW Rd,K d {24,26,28,30}, 0 ≤ K ≤ 63 PC ← PC + 1
16-bit Opcode:
1001 0110 KKdd KKKK
6.3.2 Status Register (SREG) and Boolean Formula
I T H S V N Z C
–––⇔⇔⇔⇔⇔
SN V, for signed tests.
VRdh7 R15
Set if two’s complement overflow resulted from the operation; cleared otherwise.
NR15
Set if MSB of the result is set; cleared otherwise.
ZR15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧
Set if the result is ; cleared otherwise.0x0000
CR15 Rdh7
AVR® Instruction Set Manual
Instruction Description
© 2021 Microchip Technology Inc. Manual DS40002198B-page 26
Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result) equals R[d+1]:Rd after the operation.
Example:
adiw r24,1 ; Add 1 to r25:r24
adiw ZL,63 ; Add 63 to the Z-pointer(r31:r30)
Words 1 (2 bytes)
Table 6-3. Cycles
Name Cycles
AVRe 2
AVRxm 2
AVRxt 2
AVRrc N/A
6.4 AND – Logical AND
6.4.1 Description
Performs the logical AND between the contents of register Rd and register Rr, and places the result in the destination
register Rd.
Operation:
(i) Rd ← Rd Rr
Syntax: Operands: Program Counter:
(i) AND Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1
16-bit Opcode:
0010 00rd dddd rrrr
6.4.2 Status Register (SREG) and Boolean Formula
I T H S V N Z C
– – – 0 ⇔ ⇔
SN V, for signed tests.
V0
Cleared.
NR7
Set if MSB of the result is set; cleared otherwise.
ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧
Set if the result is ; cleared otherwise.0x00
AVR® Instruction Set Manual
Instruction Description
© 2021 Microchip Technology Inc. Manual DS40002198B-page 27


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