Microchip dsPIC33EP128GS702 Manual

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 2008-2017 Microchip Technology Inc. DS70000323H-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 Features............................................................................................................................ 3

3.0 Control Registers .............................................................................................................. 4

4.0 Architecture Overview..................................................................................................... 34

5.0 Module Description ......................................................................................................... 37

6.0 PWM Generator .............................................................................................................. 48

7.0 PWM Triggers ................................................................................................................. 62

8.0 PWM Interrupts............................................................................................................... 69

9.0 PWM Operating Modes................................................................................................... 70

10.0 PWM Fault Pins .............................................................................................................. 75

11.0 Special Features ............................................................................................................. 87

12.0 PWM Output Pin Control................................................................................................. 95

13.0 Immediate Update of PWM Duty Cycle .......................................................................... 98

14.0 Power-Saving Modes...................................................................................................... 99

15.0 External Control of Individual Time Base(s) (Current Reset Mode) .............................. 100

16.0 Application Information ................................................................................................. 101

17.0 PWM Interconnects with Other Peripherals .................................................................. 115

18.0 Related Application Notes............................................................................................. 118

19.0 Revision History............................................................................................................ 119

High-Speed PWM Module

 2008-2017 Microchip Technology Inc. DS70000323H-page 3

High-Speed PWM Module

2.0 FEATURES

The High-Speed PWM module consists of the following major features:

• Up to Nine PWM Generators

• Two PWM Outputs per PWM Generator

• Individual Time Base and Duty Cycle Control for Each PWM Output

• Duty Cycle, Dead Time, Phase Shift and a Frequency Resolution of 1.04 ns

• Independent Fault and Current-Limit Inputs for All PWM Outputs

• Redundant Output

• True Independent Output

• Center-Aligned PWM mode

• Output Override Control

• Special Event Trigger

• Prescaler for Input Clock

• Dual Trigger to Analog-to-Digital Converter (ADC) per PWM Period

• PWM

L and PWM

H Output Pin Swapping

• Independent PWM Frequency, Duty Cycle and Phase-shift Changes

• Leading-Edge Blanking (LEB) Functionality

• PWM Capture Functionality

• Up to Two Master Time Bases

• Dead-Time Compensation

• PWM Chopping

• Support for Class B Protection of Fault Control Registers

Note: Duty cycle, dead time, phase shift and frequency resolution is 8.32 ns in Center-Aligned

PWM mode.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 4  2008-2017 Microchip Technology Inc.

3.0 CONTROL REGISTERS

This section outlines the specific functions of each register that controls the operation of the

High-Speed PWM module.

•PTCON: PWMx Time Base Control Register

- Enables or disables the High-Speed PWM module

- Sets the Special Event Trigger for the Analog-to-Digital Converter (ADC) and enables

or disables the primary Special Event Trigger interrupt

- Enables or disables immediate period updates

- Selects the synchronizing source for the master time base

- Specifies synchronization settings

•PTCON2: PWMx Clock Divider Select Register

- Provides the clock prescaler to all PWM time bases

•PTPER: PWMx Master Time Base Period Register

- Provides the PWM time period value

•SEVTCMP: PWMx Special Event Trigger Compare Register

- Provides the compare value that is used to trigger the ADC module and generates the

primary Special Event Trigger interrupt

•STCON: PWMx Secondary Master Time Base Control Register

- Sets the secondary Special Event Trigger for the ADC and enables or disables the

secondary Special Event Trigger interrupt

- Enables or disables immediate period updates for the secondary master time base

- Selects synchronizing source for the secondary master time base

- Specifies synchronization settings for the secondary master time base

•STCON2: PWMx Secondary Clock Divider Select Register

- Provides the clock prescaler to the PWM secondary master time base

•STPER: PWMx Secondary Master Time Base Period Register

- Provides the PWM time period value for the secondary master time base

•SSEVTCMP: PWMx Secondary Special Event Compare Register

- Provides the compare value for the secondary master time base that is used to trigger

the ADC module and generates the secondary Special Event Trigger interrupt

•CHOP: PWMx Chop Clock Generator Register

- Enables and disables the chop signal used to modulate the PWM outputs

- Specifies the period for the chop signal

•MDC: PWMx Master Duty Cycle Register

- Provides the PWM master duty cycle value

•PWMCONx: PWMx Control Register

- Enables or disables the Fault interrupt, current-limit interrupt and primary trigger interrupt

- Provides the interrupt status for the Fault interrupt, current-limit interrupt and primary

trigger interrupt

- Selects the type of time base (master time base or Independent Time Base, ITB)

- Selects the type of duty cycle (master duty cycle or independent duty cycle)

- Controls Dead-Time mode

- Enables or disables Center-Aligned mode

- Controls external PWM Reset operation

- Enables or disables immediate updates of the duty cycle, phase offset and

Independent Time Base period

•PDCx: PWMx Generator Duty Cycle Register

- Provides the duty cycle value for the PWMxH and PWMxL outputs if the master time

base is selected

- Provides the duty cycle value for the PWMxH output if the Independent Time Base is

selected

 2008-2017 Microchip Technology Inc. DS70000323H-page 5

High-Speed PWM Module

•PHASEx: PWMx Primary Phase-Shift Register

- Provides the phase-shift value for the PWMxH and/or PWMxL outputs if the master

time base is selected

- Provides the Independent Time Base period for the PWMxH and/or PWMxL outputs if

the Independent Time Base is selected

• DTRx: PWMx Dead-Time Register

- Provides the dead-time value for the PWMxH output if positive dead time is selected

- Provides the dead-time value for the PWMxL output if negative dead time is selected

•ALTDTRx: PWMx Alternate Dead-Time Register

- Provides the dead-time value for the PWMxL output if positive dead time is selected

- Provides the dead-time value for the PWMxH output if negative dead time is selected

•SDCx: PWMx Secondary Duty Cycle Register

- Provides the duty cycle value for the PWMxL output if Independent Time Base is

selected

•SPHASEx: PWMx Secondary Phase-Shift Register

- Provides the phase shift for the PWMxL output if the master time base and Independent

Output mode are selected

- Provides the Independent Time Base period value for the PWMxL output if the

Independent Time Base and Independent Output mode are selected

•TRGCONx: PWMx Trigger Control Register

- Enables the PWMx trigger postscaler start event

- Specifies the number of PWM cycles to skip before generating the first trigger

- Enables or disables the primary PWM trigger event with the secondary PWM trigger

event

•IOCONx: PWMx I/O Control Register

- Enables or disables the PWM pin control feature (PWM control or GPIO)

- Controls the PWMxH and PWMxL output polarity

- Controls the PWMxH and PWMxL output if any of the following modes are selected:

• Complementary mode

• Push-Pull mode

• True Independent mode

•FCLCONx: PWMx Fault Current-Limit Control Register

- Selects the current-limit control signal source

- Selects the current-limit polarity

- Enables or disables the Current-Limit mode

- Selects the Fault control signal source

- Configures the Fault polarity

- Enables or disables the Fault mode

•TRIGx: PWMx Primary Trigger Compare Value Register

- Provides the compare value to generate the primary PWM trigger

•STRIGx: PWMx Secondary Trigger Compare Value Register

- Provides the compare value to generate the secondary PWM trigger

•LEBCONx: PWMx Leading-Edge Blanking Control Register (Version 1)

- Selects the rising or falling edge of the PWM output for LEB

- Enables or disables LEB for Fault and current-limit inputs

•LEBCONx: PWMx Leading-Edge Blanking Control Register (Version 2)

- Selects the rising or falling edge of the PWM output for Leading-Edge Blanking (LEB)

- Enables or disables LEB for Fault and current-limit inputs

- Specifies the state of blanking for the Fault input and current-limit signals when the

selected blanking signal (PWMxH, PWMxL or other specified signal by the PWM State

Blank Source Select bits (BLANKSEL<3:0>) in the PWMx Auxiliary Control

(AUXCONx<11:8>) register) is high or low

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 6  2008-2017 Microchip Technology Inc.

•LEBDLYx: PWMx Leading-Edge Blanking Delay Register

- Specifies the blanking time for the selected Fault input and current-limit signals

•AUXCONx: PWMx Auxiliary Control Register

- Enables or disables the high-resolution PWM period and the duty cycle in order to

reduce the system power consumption

- Selects the state blanking signal for the current-limit signals and the Fault inputs

•PWMCAPx: PWMx Primary Time Base Capture Register

- Provides the captured Independent Time Base value when a leading-edge is detected

on the current-limit input

•PWMKEY: PWMx Protection Lock/Unlock Key Register

- Enables write protection of the PWMx Fault Control registers, IOCONx and FCLCONx,

for providing Class B Fault protection

 2008-2017 Microchip Technology Inc. DS70000323H-page 7

High-Speed PWM Module

R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN

(3)

— PTSIDL SESTAT SEIEN EIPU

(1)

SYNCPOL

(1, )2

SYNCOEN

(1, )2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SYNCEN

(1, )2

SYNCSRC<2:0>

(1, )2

SEVTPS<3:0>

(1)

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTEN: PWM Module Enable bit

( )3

1 = PWM module is enabled

0 = PWM module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode

0 = PWM time base runs in CPU Idle mode

bit 12 SESTAT: Special Event Trigger Interrupt Status bit

1 = Special Event Trigger interrupt is pending

0 = Special Event Trigger interrupt is not pending

This bit is cleared by setting SEIEN = 0.

bit 11 SEIEN: Special Event Trigger Interrupt Enable bit

1 = Special Event Trigger interrupt is enabled

0 = Special Event Trigger interrupt is disabled

bit 10 EIPU: Enable Immediate Period Updates bit

( )1

1 = Active Period register is updated immediately

0 = Active Period register updates occur on PWM cycle boundaries

bit 9 SYNCPOL: Synchronize Input and Output Polarity bit

( , )1 2

1 = SYNCIx/SYNCOx polarity is inverted (active-low)

0 = SYNCIx/SYNCOx is active-high

bit 8 SYNCOEN: Primary Time Base Sync Enable bit

( , )1 2

1 = SYNCOx output is enabled

0 = SYNCOx output is disabled

bit 7 SYNCEN: External Time Base Synchronization Enable bit

( , )1 2

1 = External synchronization of primary time base is enabled

0 = External synchronization of primary time base is disabled

bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits

( , )1 2

011 = SYNCI4

010 = SYNCI3

001 = SYNCI2

000 = SYNCI1

Note 1: These bits should be changed only when PTEN = 0.

2: The PWM time base synchronization must only be used in the master time base with no phase shifting.

3: When the PWM module is enabled by setting PTCON<15> = 1, a delay will be observed before the PWM

outputs start switching. This delay is equal to:

PWM Turn-on Delay = (2/ACLK) + (3  (PCLKDIV<2:0> Setting)/ACLK) + 15 ns

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 8  2008-2017 Microchip Technology Inc.

bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits

( )1

1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event

•

0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event

0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event

Note 1: These bits should be changed only when PTEN = 0.

2: The PWM time base synchronization must only be used in the master time base with no phase shifting.

3: When the PWM module is enabled by setting PTCON<15> = 1, a delay will be observed before the PWM

outputs start switching. This delay is equal to:

PWM Turn-on Delay = (2/ACLK) + (3  (PCLKDIV<2:0> Setting)/ACLK) + 15 ns

 2008-2017 Microchip Technology Inc. DS70000323H-page 9

High-Speed PWM Module

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>

( )1,2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits

( )1,2

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

2: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty

cycle, phase shift, dead time, triggers, Leading-Edge Blanking (LEB) and PWM capture.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 12  2008-2017 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>

( ,1 2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Secondary Clock Prescaler (Divider) Select bits

( , )1 2

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

2: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty

cycle, phase shift, dead time, triggers, Leading-Edge Blanking (LEB) and PWM capture.

Produkt Specifikationer

Mærke:	Microchip
Kategori:	Ikke kategoriseret
Model:	dsPIC33EP128GS702

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