Texas Instruments CD74HCT390E Manual


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CD74HC390, CDx4HCT390 High-Speed CMOS Logic Dual Decade Ripple Counter
1 Features
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4,
5, 10, 20, 25, 50, 100
Two controller reset inputs to clear each decade
counter individually
Fanout (over temperature range)
Standard outputs: 10 LSTTL loads
Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: -55°C to 125°C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
HC types
2V to 6V operation
High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5V
HCT types
4.5 V to 5.5 V operation
Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
CMOS input compatibility, II ≤ 1 μA at VOL, VOH
2 Description
The SN74HC390 and ‘HCT390 devices include two
independent 4-bit decade ripple counters, falling-edge
clocked with asynchronous clear. Each counter is
divided into two sections, a divide-by-2 and divide-
by-5 counter, each of which has an independent clock
input. This allows for very flexible configuration of the
device.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD54HCT390F3A CDIP (16) 24.38 mm × 6.92 mm
CD74HC390M SOIC (16) 9.90 mm × 3.90 mm
CD74HCT390M SOIC (16) 9.90 mm × 3.90 mm
CD74HC390E PDIP (16) 19.31 mm × 6.35 mm
CD74HCT390E PDIP (16) 19.31 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
nCLKA
nCLR
2QA2Q B2QC2QD
R R R
QQ
Q
Q
R
VCC = 16
GND = 8
nCLKB
Functional Block Diagram
CD74HC390, CD54HCT390, CD74HCT390
SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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Model: CD74HCT390E

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